代码搜索：shift
找到约 10,000 项符合「shift」的源代码
代码结果 10,000
www.eeworm.com/read/218114/4864510
m sig_shift.m
function [yshift,n]=sig_shift(x,m,n0)
%信号延迟的程序，m为输入x的下标
%n0为延迟的单位长度
n=m+n0;
yshift=x;
function [yam,n]=sig_proc(x1,n1,x2,n2,s)
%信号相加和相乘的程序
%x1，x2分别为输入序列，n1，n2为对应下标
%s=0为加法；其他值为乘法
n=min(min(
www.eeworm.com/read/216450/4893274
h fp_shift.h
/*
(c) copyright 1988 by the Vrije Universiteit, Amsterdam, The Netherlands.
See the copyright notice in the ACK home directory, in the file "Copyright".
*/
/* $Header: /cvsup/minix/src/lib/ack/f
www.eeworm.com/read/216450/4893329
h fp_shift.h
/*
(c) copyright 1988 by the Vrije Universiteit, Amsterdam, The Netherlands.
See the copyright notice in the ACK home directory, in the file "Copyright".
*/
/* $Header: /cvsup/minix/src/lib/ack/f
www.eeworm.com/read/216450/4894228
h fp_shift.h
/*
(c) copyright 1988 by the Vrije Universiteit, Amsterdam, The Netherlands.
See the copyright notice in the ACK home directory, in the file "Copyright".
*/
/* $Header: /cvsup/minix/src/lib/float
www.eeworm.com/read/203830/5037964
c bn_shift.c
/* crypto/bn/bn_shift.c */
/* Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
* All rights reserved.
*
* This package is an SSL implementation written
* by Eric Young (eay@cryptsoft.com).
www.eeworm.com/read/199094/5080521
n shift1.n
// Netlist written August 19, 2004 5:04:57 PM CST
// By FastChip Version 3.0 Build 040305-1035
// Netlist last modified August 19, 2004 5:04:57 PM CST
netlist
module SHIFT1 {
input CLK;
www.eeworm.com/read/199094/5080524
txt shift1.txt
---
--- IMPORTED MODULE [SHIFT1]
---
SOURCE
C:\\Triscend\\Projects\\ze5dev\\fcp\\Test\\EDA\\SHIFT1.EDN
DATE CREATED
Aug 19, 2004
INTERFACE
input CLK;
www.eeworm.com/read/199094/5080526
module shift1.module
module (
key = "SHIFT1",
name = "SHIFT1",
is_primitive = "false",
is_ioAdaptor = "false",
date = "Aug 19, 2004",
icon = "ImportCustom",
www.eeworm.com/read/193384/5143877
vhd shift_register.vhd
-- 库声明
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- 实体声明
entity shift_register is
-- 类属参数
generic (
TOTAL_BIT : integer := 10 );
-- 端口
port (
clk : in std_logic;
reset_n : in std_lo