代码搜索：shift
找到约 10,000 项符合「shift」的源代码
代码结果 10,000
www.eeworm.com/read/18253/782224
vhd shift_add.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity shift_add is
port(indata:in std_logic_vector(10 downto 0);
clk:in std_logic;
add_en: in std_logic;
www.eeworm.com/read/18253/782579
vhd shift8.vhd
library ieee;
use ieee.std_logic_1164.all;
entity shift8 is
port(a,clk1,clr1:in std_logic;
b:out std_logic);
end shift8;
architecture rtl of shift8 is
component dff4
port(clk,clr,d:in std_
www.eeworm.com/read/18288/783306
vhd shift_register.vhd
-- 库声明
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- 实体声明
entity shift_register is
-- 类属参数
generic (
TOTAL_BIT : integer := 10 );
-- 端口
port (
clk : in std_logic;
reset_n : in std_lo
www.eeworm.com/read/18342/784653
vhd shift_add.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity shift_add is
port(indata:in std_logic_vector(10 downto 0);
clk:in std_logic;
add_en: in std_logic;
www.eeworm.com/read/18342/784996
vhd shift8.vhd
library ieee;
use ieee.std_logic_1164.all;
entity shift8 is
port(a,clk1,clr1:in std_logic;
b:out std_logic);
end shift8;
architecture rtl of shift8 is
component dff4
port(clk,clr,d:in std_
www.eeworm.com/read/18360/785806
vhd shift_register.vhd
-- 库声明
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- 实体声明
entity shift_register is
-- 类属参数
generic (
TOTAL_BIT : integer := 10 );
-- 端口
port (
clk : in std_logic;
reset_n : in std_lo
www.eeworm.com/read/18422/787537
vhd shift_register.vhd
-- 库声明
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- 实体声明
entity shift_register is
-- 类属参数
generic (
TOTAL_BIT : integer := 10 );
-- 端口
port (
clk : in std_logic;
reset_n : in std_lo