代码搜索:shift

找到约 10,000 项符合「shift」的源代码

代码结果 10,000
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jhd shift_register.jhd

MODULE shift_register
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vhd shift_register.vhd

-- 库声明 library IEEE; use IEEE.STD_LOGIC_1164.all; -- 实体声明 entity shift_register is -- 类属参数 generic ( TOTAL_BIT : integer := 10 ); -- 端口 port ( clk : in std_logic; reset_n : in std_lo
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vhd shift_add.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity shift_add is port(indata:in std_logic_vector(10 downto 0); clk:in std_logic; add_en: in std_logic;
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vhd shift8.vhd

library ieee; use ieee.std_logic_1164.all; entity shift8 is port(a,clk1,clr1:in std_logic; b:out std_logic); end shift8; architecture rtl of shift8 is component dff4 port(clk,clr,d:in std_
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vhd shift_add.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity shift_add is port(indata:in std_logic_vector(10 downto 0); clk:in std_logic; add_en: in std_logic;
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vhd shift8.vhd

library ieee; use ieee.std_logic_1164.all; entity shift8 is port(a,clk1,clr1:in std_logic; b:out std_logic); end shift8; architecture rtl of shift8 is component dff4 port(clk,clr,d:in std_
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tdf filter_shift.tdf

parameters ( tap=16, x_wid=12 --3 ); subdesign filter_shift ( clk : input; clr : input = vcc; xin[x_wid..1] : input; s_en : input;-- = gnd; y_ff[tap..1][x_wid..1]:output;
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inc filter_shift.inc

function filter_shift ( clk, clr, xin[12..1], s_en ) returns ( y_ff[16..1][12..1] -- 16->3 );
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vhd shift_add.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity shift_add is port(indata:in std_logic_vector(10 downto 0); clk:in std_logic; add_en: in std_logic;
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vhd shift8.vhd

library ieee; use ieee.std_logic_1164.all; entity shift8 is port(a,clk1,clr1:in std_logic; b:out std_logic); end shift8; architecture rtl of shift8 is component dff4 port(clk,clr,d:in std_