代码搜索：selection
找到约 9,869 项符合「selection」的源代码
代码结果 9,869
www.eeworm.com/read/396844/2407797
m som_select.m
function varargout=som_select(c_vect,plane_h,arg)
%SOM_SELECT Manual selection of map units from a visualization.
%
% som_select(c_vect,[plane_h])
%
% som_select(3)
% som_select(sM.labels(:
www.eeworm.com/read/361261/2946905
cfg dvd.cfg
dir share/osdmenu/dvd
action key-play (0,0)
unselect unselect/barroff.png
select selection/play.png
pressed selected/play.png
end
action key-slower (0,0)
unselect unselect/barroff.png
selecte
www.eeworm.com/read/361261/2946906
cfg default.cfg
dir share/osdmenu/default
action key-play-pause (0,0)
unselect unselected.png
select selection/play_pause.png
pressed selected/play_pause.png
end
action key-stop (0,0)
unselect unselected.png
www.eeworm.com/read/267293/4268059
c uart.c
#include "config.h"
#include "regmap.h"
#include "uart.h"
extern BYTE *uart_buf;
#ifdef SUPPORT_EPP_DBG
void UART_init(BYTE selection)
{
uart_wp = uart_rp = 0;
UART_LSR = UART_SOFTRESE
www.eeworm.com/read/262041/4316916
h consolemap.h
/*
* consolemap.h
*
* Interface between console.c, selection.c and consolemap.c
*/
#define LAT1_MAP 0
#define GRAF_MAP 1
#define IBMPC_MAP 2
#define USER_MAP 3
struct vc_data;
exter
www.eeworm.com/read/159825/5580923
h scc.h
/* $Id: scc.h,v 1.29 1997/04/10 15:27:21 jreuter Exp jreuter $ */
#ifndef _SCC_H
#define _SCC_H
#include
/* selection of hardware types */
#define PA0HZP 0x00 /* hardw
www.eeworm.com/read/154076/5643086
xcp dpram_core.xcp
# Xilinx CORE Generator 5.1i
SELECT Dual_Port_Block_Memory Virtex2P Xilinx,_Inc. 4.0
CSET primitive_selection = Optimize_For_Area
CSET port_a_active_clock_edge = Rising_Edge_Triggered
CSET port_a_
www.eeworm.com/read/471424/6892535
xcp buffer_img.xcp
# Xilinx CORE Generator 6.1i
SELECT Single_Port_Block_Memory Virtex2 Xilinx,_Inc. 5.0
CSET primitive_selection = Optimize_For_Area
CSET init_value = 0
CSET register_inputs = false
CSET write_enable_po
www.eeworm.com/read/471424/6892539
xcp tabla_q.xcp
# Xilinx CORE Generator 6.1i
SELECT Single_Port_Block_Memory Virtex2 Xilinx,_Inc. 5.0
CSET primitive_selection = Optimize_For_Area
CSET init_value = 0
CSET register_inputs = false
CSET write_enable_po
www.eeworm.com/read/471424/6892540
xcp buffer_comp_chrom.xcp
# Xilinx CORE Generator 6.1i
SELECT Single_Port_Block_Memory Virtex2 Xilinx,_Inc. 5.0
CSET primitive_selection = Optimize_For_Area
CSET init_value = 0
CSET register_inputs = false
CSET write_enable_po