代码搜索：selection

找到约 9,869 项符合「selection」的源代码

代码结果 9,869
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/160189/10559790

xcp tabla_q.xcp

# Xilinx CORE Generator 6.1i SELECT Single_Port_Block_Memory Virtex2 Xilinx,_Inc. 5.0 CSET primitive_selection = Optimize_For_Area CSET init_value = 0 CSET register_inputs = false CSET write_enable_po
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www.eeworm.com/read/160189/10559793

xcp buffer_comp_chrom.xcp

# Xilinx CORE Generator 6.1i SELECT Single_Port_Block_Memory Virtex2 Xilinx,_Inc. 5.0 CSET primitive_selection = Optimize_For_Area CSET init_value = 0 CSET register_inputs = false CSET write_enable_po
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www.eeworm.com/read/160189/10559820

xcp q_rom.xcp

# Xilinx CORE Generator 6.1i SELECT Single_Port_Block_Memory Virtex2 Xilinx,_Inc. 5.0 CSET primitive_selection = Optimize_For_Area CSET init_value = 0 CSET register_inputs = false CSET write_enable_po
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www.eeworm.com/read/160189/10559848

xcp buffer_comp.xcp

# Xilinx CORE Generator 6.1i SELECT Single_Port_Block_Memory Virtex2 Xilinx,_Inc. 5.0 CSET primitive_selection = Optimize_For_Area CSET init_value = 0 CSET register_inputs = false CSET write_enable_po
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www.eeworm.com/read/160189/10559942

xcp huff_rom.xcp

# Xilinx CORE Generator 6.1i SELECT Single_Port_Block_Memory Virtex2 Xilinx,_Inc. 5.0 CSET primitive_selection = Optimize_For_Area CSET init_value = 0 CSET register_inputs = false CSET write_enable_po
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www.eeworm.com/read/420899/10769044

h spi.h

#ifndef __SPI_H__ #define __SPI_h__ #include "dma.h" #define SPI_TX_FIFO_SIZE 64 #define SPI_RX_FIFO_SIZE 64 #define SPI_NORMAL_DMA // normal DMA or SDMA Selection. #define SPI_INT_TRA
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www.eeworm.com/read/367965/7808615

h spi.h

#ifndef __SPI_H__ #define __SPI_h__ #include "dma.h" #define SPI_TX_FIFO_SIZE 64 #define SPI_RX_FIFO_SIZE 64 #define SPI_NORMAL_DMA // normal DMA or SDMA Selection. #define SPI_INT_TRA
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www.eeworm.com/read/397115/8066671

m som_select.m

function varargout=som_select(c_vect,plane_h,arg) %SOM_SELECT Manual selection of map units from a visualization. % % som_select(c_vect,[plane_h]) % % som_select(3) % som_select(sM.labels(:
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www.eeworm.com/read/332117/12777655

xcp buffer_img.xcp

# Xilinx CORE Generator 6.1i SELECT Single_Port_Block_Memory Virtex2 Xilinx,_Inc. 5.0 CSET primitive_selection = Optimize_For_Area CSET init_value = 0 CSET register_inputs = false CSET write_enab
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www.eeworm.com/read/332117/12777682

xcp tabla_q.xcp

# Xilinx CORE Generator 6.1i SELECT Single_Port_Block_Memory Virtex2 Xilinx,_Inc. 5.0 CSET primitive_selection = Optimize_For_Area CSET init_value = 0 CSET register_inputs = false CSET write_enab
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