代码搜索：second
找到约 10,000 项符合「second」的源代码
代码结果 10,000
www.eeworm.com/read/406252/11446028
bsf second.bsf
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to
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png second.png
www.eeworm.com/read/402966/11525844
scf second.scf
www.eeworm.com/read/402966/11525853
vhd second.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity second is
port(clk,clr:in std_logic;
sec1,sec0:out std_logic_vector(3 downto 0);
co:out std_logic);
end second
www.eeworm.com/read/402327/11537118
sym second.sym
www.eeworm.com/read/402327/11537119
tdf second.tdf
SUBDESIGN second
(
clk,reset,setmin :INPUT;
daout[6..0],enmin :OUTPUT;
)
VARIABLE
count[6..0],s,sh: DFF;
BEGIN
count[].clk=clk;
count[].clrn=reset;
daout[]=count[].q;
www.eeworm.com/read/402133/11542383
sym second.sym
www.eeworm.com/read/402133/11542411
tdf second.tdf
SUBDESIGN second
(
clk,reset,setmin :INPUT;
daout[6..0],enmin :OUTPUT;
)
VARIABLE
count[6..0],s,sh: DFF;
BEGIN
count[].clk=clk;
count[].clrn=reset;
daout[]=count[].q;
www.eeworm.com/read/402018/11543936
vhd second.vhd
library ieee;
use ieee.std_logic_1164.all;
entity second is
port(a,b,c,zin,yin:in std_logic;
dout,eout,fout,gout:out std_logic);
end second;
architecture rtl of second is
begin
www.eeworm.com/read/401210/11562000