代码搜索:proc

找到约 10,000 项符合「proc」的源代码

代码结果 10,000
www.eeworm.com/read/449996/7492104

h proc.h

#ifndef _PROC_H #define _PROC_H #include #ifndef _MBUF_H #include "mbuf.h" #endif #ifndef _TIMER_H #include "timer.h" #endif #define SIGQSIZE 200 /* Entries in ksignal queu
www.eeworm.com/read/449577/7500262

proc roi.proc

use1dopp=1 mean_pixel_rng = 3100 ymin = 0 #ymax = 40000
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c if_proc.c

/* Interface name and statistics get function using proc file system * Copyright (C) 1999 Kunihiro Ishiguro * * This file is part of GNU Zebra. * * GNU Zebra is free software; you can redistribut
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po if_proc.po

if_proc.o: if_proc.c ../lib/zebra.h ../config.h \ /opt/eldk/eldk_3.1.1/ppc_8xx/usr/include/unistd.h \ /opt/eldk/eldk_3.1.1/ppc_8xx/usr/include/features.h \ /opt/eldk/eldk_3.1.1/ppc_8xx/usr/inclu
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o if_proc.o

www.eeworm.com/read/445084/7599624

h proc.h

/* * Copyright 2002 by Texas Instruments Incorporated. * All rights reserved. Property of Texas Instruments Incorporated. * Restricted rights to use, duplicate or disclose this code are *
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doc proc.doc

www.eeworm.com/read/437619/7744875

h proc.h

#ifndef _PROC_H #define _PROC_H #include #ifndef _MBUF_H #include "mbuf.h" #endif #ifndef _TIMER_H #include "timer.h" #endif #define SIGQSIZE 200 /* Entries in ksignal queu
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v proc.v

// MAX+plus II Verilog Example // Combinatorial Always Statement // Copyright (c) 1994 Altera Corporation module proc (d, q); input [2:0] d; output [1:0] q; integer num_bits;
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vhd proc.vhd

-- MAX+plus II VHDL Example -- Combinatorial Process Statement -- Copyright (c) 1994 Altera Corporation ENTITY proc IS PORT ( d : IN BIT_VECTOR (2 DOWNTO 0); q : OUT INTEGER RANGE 0 TO