代码搜索：parameter
找到约 10,000 项符合「parameter」的源代码
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www.eeworm.com/read/300836/13890025
xct wash.xct
[Compiler Settings]
Strategy = Delay
Maximum GLB Inputs = 16
Maximum GLB Outputs = 4
Carry Pin Direction = FALSE
Perform Timing Analysis = TRUE
Ignore Reserved Pins = FALSE
Minimize GLB Levels
www.eeworm.com/read/238364/13891573
m chap3_6.m
%Fuzzy Tunning PID Control
clear all;
close all;
a=newfis('fuzzpid');
a=addvar(a,'input','e',[-3,3]); %Parameter e
a=addmf(a,'input',1,'NB','zmf',[-3,-1]);
a=addmf(a,'
www.eeworm.com/read/238364/13891578
m chap3_4.m
%Fuzzy Controller
clear all;close all;
a=newfis('fuzz_ljk');
f1=1.0;
a=addvar(a,'input','e',[-3*f1,3*f1]); % Parameter e
a=addmf(a,'input',1,'NB','zmf',[-3*f1,-1*f1]);
a=
www.eeworm.com/read/238364/13891598
m chap3_7.m
%Fuzzy Immune PID Control
clear all;
close all;
a=newfis('fuzz_ljk');
f1=10;
a=addvar(a,'input','u',[-f1*1,f1*1]); %Parameter e
a=addmf(a,'input',1,'NB','zmf',[-f1*1,f1*1]);
a=a
www.eeworm.com/read/238364/13891604
m chap3_3.m
%Fuzzy Controller
clear all;
close all;
a=newfis('fuzzf');
f1=1;
a=addvar(a,'input','e',[-3*f1,3*f1]); %Parameter e
a=addmf(a,'input',1,'NB','zmf',[-3*f1,-1*f1]);
a=addmf(a,'inpu
www.eeworm.com/read/300713/13897186
v wave2.v
`timescale 10ns/1ns
module wave2;
reg wave;
parameter cycle=5;
initial
fork
wave=0;
#(cycle) wave=1;
#(2*cycle) wave=0;
#(3*cycle) wave=1;
#(4*cycle) wave=0;
#(5*cycle) wave=
www.eeworm.com/read/300713/13897194
v adder.v
module adder(cout,sum,a,b,cin);
parameter size=16;
output cout;
output[size-1:0] sum;
input cin;
input[size-1:0] a,b;
assign {cout,sum}=a+b+cin;
endmodule
www.eeworm.com/read/300713/13897212
v wave1.v
`timescale 10ns/1ns
module wave1;
reg wave;
parameter cycle=10;
initial
begin
wave=0;
#(cycle/2) wave=1;
#(cycle/2) wave=0;
#(cycle/2) wave=1;
#(cycle/2) wave=0;
#(cycle/2
www.eeworm.com/read/300713/13897333
v rom.v
module ROM(addr,data,oe);
output[7:0] data;
input[14:0] addr;
input oe;
reg[7:0] mem[0:255];
parameter DELAY = 100;
assign #DELAY data=(oe==0) ? mem[addr] : 8'hzz;
initial $readmemh("rom.he
www.eeworm.com/read/300713/13897341
v test2.v
module test2;
reg clk1,clk2;
parameter CYCLE = 100;
always
begin
{clk1,clk2} = 2'b10;
#(CYCLE/4) {clk1,clk2} = 2'b01;
#(CYCLE/4) {clk1,clk2} = 2'b11;
#(CYCLE/4) {clk1,clk2} =