代码搜索:parameter

找到约 10,000 项符合「parameter」的源代码

代码结果 10,000
www.eeworm.com/read/153981/11996793

c 2410lib.c

/**************************************************************************** 【文 件 名 称】2410lib.c 【功 能 描 述】FS2410XP教学平台实验程序 【程 序 版 本】3.0 【创建及创建日期】优龙公司/2005-XX-XX 【修改及修改日期】2005-5-23 *****
www.eeworm.com/read/256461/11998824

v wave2.v

`timescale 10ns/1ns module wave2; reg wave; parameter cycle=5; initial fork wave=0; #(cycle) wave=1; #(2*cycle) wave=0; #(3*cycle) wave=1; #(4*cycle) wave=0; #(5*cycle) wave=
www.eeworm.com/read/256461/11998828

v adder.v

module adder(cout,sum,a,b,cin); parameter size=16; output cout; output[size-1:0] sum; input cin; input[size-1:0] a,b; assign {cout,sum}=a+b+cin; endmodule
www.eeworm.com/read/256461/11998849

v wave1.v

`timescale 10ns/1ns module wave1; reg wave; parameter cycle=10; initial begin wave=0; #(cycle/2) wave=1; #(cycle/2) wave=0; #(cycle/2) wave=1; #(cycle/2) wave=0; #(cycle/2
www.eeworm.com/read/256461/11998928

v rom.v

module ROM(addr,data,oe); output[7:0] data; input[14:0] addr; input oe; reg[7:0] mem[0:255]; parameter DELAY = 100; assign #DELAY data=(oe==0) ? mem[addr] : 8'hzz; initial $readmemh("rom.he
www.eeworm.com/read/256461/11998933

v test2.v

module test2; reg clk1,clk2; parameter CYCLE = 100; always begin {clk1,clk2} = 2'b10; #(CYCLE/4) {clk1,clk2} = 2'b01; #(CYCLE/4) {clk1,clk2} = 2'b11; #(CYCLE/4) {clk1,clk2} =
www.eeworm.com/read/256461/11999107

v count4_tp.v

`timescale 1ns/1ns `include "count4.v" module coun4_tp; reg clk,reset; wire[3:0] out; parameter DELY=100; count4 mycount(out,reset,clk); always #(DELY/2) clk = ~clk; initial begin clk =0
www.eeworm.com/read/342759/12002070

html slide011.html

www.eeworm.com/read/153764/12008442

h plzero.h

////////////////////////////////////////////////////////////////////////////// // // plzero.h // // Global header file. This file should only contain information that // is relevant to all the modules
www.eeworm.com/read/256292/12010379

v count4_tp.v

`timescale 1ns/1ns `include "count4.v" module coun4_tp; reg clk,reset; wire[3:0] out; parameter DELY=100; count4 mycount(out,reset,clk); always #(DELY/2) clk = ~clk; initial begin clk =0