代码搜索：parameter
找到约 10,000 项符合「parameter」的源代码
代码结果 10,000
www.eeworm.com/read/155166/11892811
m kparm.m
% kparm.m - Kaiser window parameters for filter design.
%
% [alpha, N] = kparm(DF, A)
%
% alpha = window shape parameter
% N = window length (odd)
% DF = Df/fs = transition width in units of fs
% A =
www.eeworm.com/read/344233/11898303
c 1820.c
#include "define.h"
#include "1820.h"
#include
#define uchar unsigned char
#define uint unsigned int
sbit dq = P3^4;
bit flag;
uint Temperature;
uchar temp_buff[9]; //存储读取的字节，
www.eeworm.com/read/154996/11907539
m awgn.m
%*************************************************************************************
% This function pertains to the addition of AWGN with mean zero and
% parameter 'variance' to
www.eeworm.com/read/154977/11908596
asm dac41out.asm
;File: dac41out.a51
;Author: Eckart Hartmann Date:15/10/2003
;Development progress: Dac841.df
;
;DacOut==========Output a value on DAC.
;C Function prototype: char DacOut(char cChan, int iDac);
www.eeworm.com/read/257336/11933493
v wave2.v
`timescale 10ns/1ns
module wave2;
reg wave;
parameter cycle=5;
initial
fork
wave=0;
#(cycle) wave=1;
#(2*cycle) wave=0;
#(3*cycle) wave=1;
#(4*cycle) wave=0;
#(5*cycle) wave=
www.eeworm.com/read/257336/11933495
v adder.v
module adder(cout,sum,a,b,cin);
parameter size=16;
output cout;
output[size-1:0] sum;
input cin;
input[size-1:0] a,b;
assign {cout,sum}=a+b+cin;
endmodule
www.eeworm.com/read/257336/11933525
v wave1.v
`timescale 10ns/1ns
module wave1;
reg wave;
parameter cycle=10;
initial
begin
wave=0;
#(cycle/2) wave=1;
#(cycle/2) wave=0;
#(cycle/2) wave=1;
#(cycle/2) wave=0;
#(cycle/2
www.eeworm.com/read/257336/11933619
v rom.v
module ROM(addr,data,oe);
output[7:0] data;
input[14:0] addr;
input oe;
reg[7:0] mem[0:255];
parameter DELAY = 100;
assign #DELAY data=(oe==0) ? mem[addr] : 8'hzz;
initial $readmemh("rom.he
www.eeworm.com/read/257336/11933629
v test2.v
module test2;
reg clk1,clk2;
parameter CYCLE = 100;
always
begin
{clk1,clk2} = 2'b10;
#(CYCLE/4) {clk1,clk2} = 2'b01;
#(CYCLE/4) {clk1,clk2} = 2'b11;
#(CYCLE/4) {clk1,clk2} =
www.eeworm.com/read/257336/11933766
v count4_tp.v
`timescale 1ns/1ns
`include "count4.v"
module coun4_tp;
reg clk,reset;
wire[3:0] out;
parameter DELY=100;
count4 mycount(out,reset,clk);
always #(DELY/2) clk = ~clk;
initial
begin
clk =0