代码搜索：parameter
找到约 10,000 项符合「parameter」的源代码
代码结果 10,000
www.eeworm.com/read/481648/6636858
v wave1.v
`timescale 10ns/1ns
module wave1;
reg wave;
parameter cycle=10;
initial
begin
wave=0;
#(cycle/2) wave=1;
#(cycle/2) wave=0;
#(cycle/2) wave=1;
#(cycle/2) wave=0;
#(cycle/2
www.eeworm.com/read/481648/6636903
v rom.v
module ROM(addr,data,oe);
output[7:0] data;
input[14:0] addr;
input oe;
reg[7:0] mem[0:255];
parameter DELAY = 100;
assign #DELAY data=(oe==0) ? mem[addr] : 8'hzz;
initial $readmemh("rom.he
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v test2.v
module test2;
reg clk1,clk2;
parameter CYCLE = 100;
always
begin
{clk1,clk2} = 2'b10;
#(CYCLE/4) {clk1,clk2} = 2'b01;
#(CYCLE/4) {clk1,clk2} = 2'b11;
#(CYCLE/4) {clk1,clk2} =
www.eeworm.com/read/481648/6636958
v count4_tp.v
`timescale 1ns/1ns
`include "count4.v"
module coun4_tp;
reg clk,reset;
wire[3:0] out;
parameter DELY=100;
count4 mycount(out,reset,clk);
always #(DELY/2) clk = ~clk;
initial
begin
clk =0
www.eeworm.com/read/481652/6636968
v dff.v
/******************************************************/
module pDFF(DATA,QOUT,CLOCK,RESET);
/******************************************************/
parameter WIDTH = 1;
input [WIDTH-1:0] D
www.eeworm.com/read/481781/6638285
txt dsl.txt
4.8
module shifter(din,clk,clr,dout);
`define size 7
input din,clk,clr;
output[`size:0]dout;
reg[`size:0]dout;
always@(posedge clk)
begin
if(clr) dout=0;
else
begin
dou
www.eeworm.com/read/481426/6640688
v m5.v
//5阶m序列
module m5
(
clk,
mout);
input clk;
output mout;
reg [4:0]cnt;
reg mout;
wire [4:0]d;
assign d[3:0]=cnt[4:1];
assign d[4]=cnt[2]^cnt[0]; //计算生成多项式
parameter mo=5'b1111
www.eeworm.com/read/480425/6663685
rpt dds.map.rpt
Analysis & Synthesis report for dds
Fri May 08 23:20:33 2009
Quartus II Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Full Version
---------------------
; Table of Contents ;
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bsf dds.bsf
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to