代码搜索：out_data
找到约 581 项符合「out_data」的源代码
代码结果 581
www.eeworm.com/read/178151/9417483
c two_cpu.c
#include
#include
#define uchar unsigned char
#define uint unsigned int
uchar x=0x0000;
uchar y=0x65;
uchar in_data;
uchar xdata out_data=0x52;
main()
{
while(1)
{XBYTE[x
www.eeworm.com/read/177199/9465583
java e10_4.java
import java.io.*;
public class E10_4
{public static void main(String args[])
{try
{FileOutputStream fos=new FileOutputStream("jerry.dat");
DataOutputStream out_data=new DataOutputS
www.eeworm.com/read/372505/9507523
v reg8.v
module reg8(out_data,in_data,clk,clr);
output[7:0] out_data;
input[7:0] in_data;
input clk,clr;
reg[7:0] out_data;
always @(posedge clk or posedge clr)
begin
if(clr) out_data
www.eeworm.com/read/169659/9847502
c ads1110.c
/*
file name:ads1110.c
head file:ads1110.h delay.h
说明：
chip：mega16L
编译器：CodeVisionAVR C Compiler
在ADS1100测试通过
i2c程序包包括：
void io_dir(uchar dir);
void ads1100
www.eeworm.com/read/169659/9847505
c~ ads1110.c~
/*
file name:ads1110.c
head file:ads1110.h delay.h
说明：
chip：mega16L
编译器：CodeVisionAVR C Compiler
在ADS1100测试通过
i2c程序包包括：
void io_dir(uchar dir);
void ads1100
www.eeworm.com/read/169221/9874946
v reg8.v
module reg8(out_data,in_data,clk,clr);
output[7:0] out_data;
input[7:0] in_data;
input clk,clr;
reg[7:0] out_data;
always @(posedge clk or posedge clr)
begin
if(clr) out_data
www.eeworm.com/read/363143/9966539
h median_3x3.h
/* ------------------------------------------------------------------------ */
/* 2006.02 for DSP training lab */
/* ==============================================
www.eeworm.com/read/362310/10005860
v reg8.v
module reg8(out_data,in_data,clk,clr);
output[7:0] out_data;
input[7:0] in_data;
input clk,clr;
reg[7:0] out_data;
always @(posedge clk or posedge clr)
begin
if(clr) out_data