代码搜索：out_data
找到约 581 项符合「out_data」的源代码
代码结果 581
www.eeworm.com/read/384201/8891105
v reg8.v
module reg8(out_data,in_data,clk,clr);
output[7:0] out_data;
input[7:0] in_data;
input clk,clr;
reg[7:0] out_data;
always @(posedge clk or posedge clr)
begin
if(clr) out_data
www.eeworm.com/read/383822/8915519
v reg8.v
module reg8(out_data,in_data,clk,clr);
output[7:0] out_data;
input[7:0] in_data;
input clk,clr;
reg[7:0] out_data;
always @(posedge clk or posedge clr)
begin
if(clr) out_data
www.eeworm.com/read/427377/8949287
h spreading.h
/*
|
| Copyright disclaimer:
| This software was developed at the National Institute of Standards
| and Technology by employees of the Federal Government in the course
| of their official d
www.eeworm.com/read/426557/9013486
v filter.v
//`include "reg8.v"
module filter(out_data,in_data,clk);
output[9:0] out_data;
input [7:0] in_data;
input clk;
//reg[9:0] out_data;
wire clr,en;
assign en=1;assign clr=0;
reg[7:0] in_data1
www.eeworm.com/read/426557/9013618
wsf wed.wsf
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to
www.eeworm.com/read/426557/9013746
bak reg8.v.bak
module reg8(out_data,in_data,clk,clr);
output[7:0] out_data;
input [7:0] in_data;
input clk,clr;
www.eeworm.com/read/426557/9013752
v reg8.v
module reg8(out_data,in_data,clk,clr);
output[7:0] out_data;
input [7:0] in_data;
input clk,clr;
www.eeworm.com/read/184529/9096072
h spreading.h
/*
|
| Copyright disclaimer:
| This software was developed at the National Institute of Standards
| and Technology by employees of the Federal Government in the course
| of their official d
www.eeworm.com/read/378479/9229734
v reg8.v
module reg8(out_data,in_data,clk,clr);
output[7:0] out_data;
input[7:0] in_data;
input clk,clr;
reg[7:0] out_data;
always @(posedge clk or posedge clr)
begin
if(clr) out_data
www.eeworm.com/read/374228/9415389
v reg8.v
module reg8(out_data,in_data,clk,clr);
output[7:0] out_data;
input[7:0] in_data;
input clk,clr;
reg[7:0] out_data;
always @(posedge clk or posedge clr)
begin
if(clr) out_data