代码搜索：out_data
找到约 581 项符合「out_data」的源代码
代码结果 581
www.eeworm.com/read/433620/7918267
rpt clock.fit.rpt
Fitter report for clock
Thu Mar 05 19:28:00 2009
Version 6.0 Build 178 04/27/2006 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Fi
www.eeworm.com/read/433620/7918315
pin clock.pin
-- Copyright (C) 1991-2006 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and a
www.eeworm.com/read/297875/7990827
v reg8.v
module reg8(out_data,in_data,clk,clr);
output[7:0] out_data;
input[7:0] in_data;
input clk,clr;
reg[7:0] out_data;
always @(posedge clk or posedge clr)
begin
if(clr) out_data
www.eeworm.com/read/297690/8004458
asm para_tab.asm
.def _Out_Data
.global _Out_Data
.text
_Out_Data:
.word 10h,11h,12h,13h,14h,15h,16h,17h,18h,19h
.word 1
www.eeworm.com/read/296104/8121693
v reg8.v
module reg8(out_data,in_data,clk,clr);
output[7:0] out_data;
input[7:0] in_data;
input clk,clr;
reg[7:0] out_data;
always @(posedge clk or posedge clr)
begin
if(clr) out_data
www.eeworm.com/read/296097/8122187
v reg8.v
module reg8(out_data,in_data,clk,clr);
output[7:0] out_data;
input[7:0] in_data;
input clk,clr;
reg[7:0] out_data;
always @(posedge clk or posedge clr)
begin
if(clr) out_data
www.eeworm.com/read/244507/12859141
v reg8.v
module reg8(out_data,in_data,clk,clr);
output[7:0] out_data;
input[7:0] in_data;
input clk,clr;
reg[7:0] out_data;
always @(posedge clk or posedge clr)
begin
if(clr) out_data
www.eeworm.com/read/143521/12868145
v reg8.v
module reg8(out_data,in_data,clk,clr);
output[7:0] out_data;
input[7:0] in_data;
input clk,clr;
reg[7:0] out_data;
always @(posedge clk or posedge clr)
begin
if(clr) out_data