代码搜索：optimize

找到约 6,026 项符合「optimize」的源代码

代码结果 6,026
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/364157/9920159

xcp buffer_comp.xcp

# Xilinx CORE Generator 6.1i SELECT Single_Port_Block_Memory Virtex2 Xilinx,_Inc. 5.0 CSET primitive_selection = Optimize_For_Area CSET init_value = 0 CSET register_inputs = false CSET write_enable_po
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www.eeworm.com/read/364157/9920188

xcp huff_rom.xcp

# Xilinx CORE Generator 6.1i SELECT Single_Port_Block_Memory Virtex2 Xilinx,_Inc. 5.0 CSET primitive_selection = Optimize_For_Area CSET init_value = 0 CSET register_inputs = false CSET write_enable_po
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www.eeworm.com/read/165787/10051491

src init_7820.src

; .\init_7820.SRC generated from: init_7820.c ; COMPILER INVOKED BY: ; C:\KEIL\C51\BIN\C51.EXE init_7820.c OPTIMIZE(0,SPEED) BROWSE DEBUG OBJECTEXTEND SRC(.\init_7820.SRC) NAME INIT_7820
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www.eeworm.com/read/165787/10051549

src init_7860.src

; .\init_7860.SRC generated from: init_7860.c ; COMPILER INVOKED BY: ; C:\KEIL\C51\BIN\C51.EXE init_7860.c OPTIMIZE(0,SPEED) BROWSE DEBUG OBJECTEXTEND SRC(.\init_7860.SRC) NAME INIT_7860
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www.eeworm.com/read/358122/10195799

tmp link.lnk.tmp

-d"./settings/STM32F10x.lsl" --optimize=0 --map-file-format=2 .\objects\cortexm3_macro.obj .\objects\cstart_thumb2.obj .\objects\inithardware.obj .\objects\initvectortable.obj .\objects\main.obj .\
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www.eeworm.com/read/423692/10537313

mpf zuixiaoxitong.mpf

[Project] Format=0 Alias="zuixiaoxitong" HeadPath="" [Source/ZLG7289.c] FileType=2 BankNumb=0 FileTime="01C82514-AFDB0800" ObjTime="01C82E63-42F8C9E0" ExcludeBuild=FALSE Debug=TRUE Optimize
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www.eeworm.com/read/160189/10559760

xcp buffer_img.xcp

# Xilinx CORE Generator 6.1i SELECT Single_Port_Block_Memory Virtex2 Xilinx,_Inc. 5.0 CSET primitive_selection = Optimize_For_Area CSET init_value = 0 CSET register_inputs = false CSET write_enable_po
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www.eeworm.com/read/160189/10559790

xcp tabla_q.xcp

# Xilinx CORE Generator 6.1i SELECT Single_Port_Block_Memory Virtex2 Xilinx,_Inc. 5.0 CSET primitive_selection = Optimize_For_Area CSET init_value = 0 CSET register_inputs = false CSET write_enable_po
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www.eeworm.com/read/160189/10559793

xcp buffer_comp_chrom.xcp

# Xilinx CORE Generator 6.1i SELECT Single_Port_Block_Memory Virtex2 Xilinx,_Inc. 5.0 CSET primitive_selection = Optimize_For_Area CSET init_value = 0 CSET register_inputs = false CSET write_enable_po
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www.eeworm.com/read/160189/10559820

xcp q_rom.xcp

# Xilinx CORE Generator 6.1i SELECT Single_Port_Block_Memory Virtex2 Xilinx,_Inc. 5.0 CSET primitive_selection = Optimize_For_Area CSET init_value = 0 CSET register_inputs = false CSET write_enable_po
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