代码搜索：optimize

找到约 6,026 项符合「optimize」的源代码

代码结果 6,026
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/411052/2192382

makefile_mmc2

PRG = avr_mmc2 OBJ = main2.o uart.o xitoa.o stime.o tff.o mmc.o MCU_TARGET = atmega64 OPTIMIZE = -Os -mcall-prologues DEFS = LIBS = DEBUG =
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www.eeworm.com/read/411052/2192383

makefile_cfc2

PRG = avr_cfc2 OBJ = main2.o uart.o xitoa.o stime.o tff.o cfc.o MCU_TARGET = atmega64 OPTIMIZE = -Os -mcall-prologues DEFS = LIBS = DEBUG =
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www.eeworm.com/read/395929/2429598

s roundmode.s

.code .align 4 .IMPORT foo,data ; Switch in/out of different rounding modes. ; Also make sure we "optimize" away useless rounding mode relocations addil LR'foo-0x12345,%r27 ldo RR'foo-0x12345
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www.eeworm.com/read/383940/2607834

h xe1205debug.h

uint8_t var; uint16_t lasterr; void xe1205error(uint8_t loc, uint8_t value_) __attribute__ ((noinline)) { // this is just to make sure the compiler doesn't optimize // out calls to this functio
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www.eeworm.com/read/260612/4329903

tdf scfifo_eaq.tdf

--scfifo DEVICE_FAMILY=Stratix LPM_NUMWORDS=16 LPM_SHOWAHEAD=OFF lpm_width=8 OPTIMIZE_FOR_SPEED=5 OVERFLOW_CHECKING=ON UNDERFLOW_CHECKING=ON USE_EAB=ON aclr clock data empty full q rdreq usedw wrreq A
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www.eeworm.com/read/260612/4329921

tdf scfifo_nbq.tdf

--scfifo DEVICE_FAMILY=Stratix LPM_NUMWORDS=16 LPM_SHOWAHEAD=OFF lpm_width=10 OPTIMIZE_FOR_SPEED=5 OVERFLOW_CHECKING=ON UNDERFLOW_CHECKING=ON USE_EAB=ON aclr clock data empty full q rdreq usedw wrreq
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www.eeworm.com/read/258653/4352700

am makefile.am

include $(top_srcdir)/misc/Makefile.common LIBTOOL = $(SHELL) $(top_builddir)/libtool EXTRA_DIST = stubs.s wrapper.S noinst_LTLIBRARIES = $(wine_lib) AM_CFLAGS = $(X_CFLAGS) @W32_NO_OPTIMIZE@ \ -
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www.eeworm.com/read/431720/8660157

tdf scfifo_1eu.tdf

--scfifo ADD_RAM_OUTPUT_REGISTER="OFF" DEVICE_FAMILY="Cyclone II" LPM_NUMWORDS=128 LPM_SHOWAHEAD="OFF" lpm_width=8 lpm_widthu=7 OPTIMIZE_FOR_SPEED=5 OVERFLOW_CHECKING="ON" UNDERFLOW_CHECKING="ON" USE_
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www.eeworm.com/read/430383/8752077

xcp buffer_img.xcp

# Xilinx CORE Generator 6.1i SELECT Single_Port_Block_Memory Virtex2 Xilinx,_Inc. 5.0 CSET primitive_selection = Optimize_For_Area CSET init_value = 0 CSET register_inputs = false CSET write_enable_po
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www.eeworm.com/read/430383/8752103

xcp tabla_q.xcp

# Xilinx CORE Generator 6.1i SELECT Single_Port_Block_Memory Virtex2 Xilinx,_Inc. 5.0 CSET primitive_selection = Optimize_For_Area CSET init_value = 0 CSET register_inputs = false CSET write_enable_po
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