代码搜索：opcode
找到约 2,963 项符合「opcode」的源代码
代码结果 2,963
www.eeworm.com/read/297875/7990865
v alu.v
`define add 3'd0
`define minus 3'd1
`define band 3'd2
`define bor 3'd3
`define bnot 3'd4
module alu(out,opcode,a,b);
output[7:0] out;
reg[7:0] out;
input[2:0] opcode;
input[7:0] a,b;
alway
www.eeworm.com/read/297703/8002866
v alu.v
`define add 3'd0
`define minus 3'd1
`define band 3'd2
`define bor 3'd3
`define bnot 3'd4
module alu(out,opcode,a,b);
output[7:0] out;
reg[7:0] out;
input[2:0] opcode;
input[7:0] a,b;
alway
www.eeworm.com/read/397984/8011765
c asfpga.c
/*
asfpga version 1.00e
====================
asfpga is an assembler written for use in FPGA design. It can be easily modified
for your instruction set. The ultimate goal of this software is to all
www.eeworm.com/read/296104/8121730
v alu.v
`define add 3'd0
`define minus 3'd1
`define band 3'd2
`define bor 3'd3
`define bnot 3'd4
module alu(out,opcode,a,b);
output[7:0] out;
reg[7:0] out;
input[2:0] opcode;
input[7:0] a,b;
alway
www.eeworm.com/read/296097/8122238
v alu.v
`define add 3'd0
`define minus 3'd1
`define band 3'd2
`define bor 3'd3
`define bnot 3'd4
module alu(out,opcode,a,b);
output[7:0] out;
reg[7:0] out;
input[2:0] opcode;
input[7:0] a,b;
alway
www.eeworm.com/read/247283/12668122
awk opcodedoc.awk
#
# Extract opcode documentation for sqliteVdbe.c and generate HTML
#
BEGIN {
print ""
print "SQLite Virtual Database Engine Opcodes"
print ""
}
/ Opcod
www.eeworm.com/read/332694/12743653
cls excelfile.cls
VERSION 1.0 CLASS
BEGIN
MultiUse = -1 'True
Persistable = 0 'NotPersistable
DataBindingBehavior = 0 'vbNone
DataSourceBehavior = 0 'vbNone
MTSTransactionMode = 0 'NotAnMTSObject
www.eeworm.com/read/144833/12770518
m wavework.m
function [varargout] = wavework(opcode,type,c,s,n,x)
error(nargchk(4,6,nargin));
if (ndims(c) ~= 2)|(size(c,1) ~= 1)
error('C must be a row vector.');
end
if (ndims(s) ~=2)| ~isreal(s)|~isnum
www.eeworm.com/read/244507/12859181
v alu.v
`define add 3'd0
`define minus 3'd1
`define band 3'd2
`define bor 3'd3
`define bnot 3'd4
module alu(out,opcode,a,b);
output[7:0] out;
reg[7:0] out;
input[2:0] opcode;
input[7:0] a,b;
alway
www.eeworm.com/read/143521/12868166
v alu.v
`define add 3'd0
`define minus 3'd1
`define band 3'd2
`define bor 3'd3
`define bnot 3'd4
module alu(out,opcode,a,b);
output[7:0] out;
reg[7:0] out;
input[2:0] opcode;
input[7:0] a,b;
alway