代码搜索：opcode
找到约 2,963 项符合「opcode」的源代码
代码结果 2,963
www.eeworm.com/read/221574/4828216
h save.h
/* Write the data from the opcode */
switch (inst.code.save) {
/* Byte */
case S_C_Eb:
inst_op1_b=inst.cond ? 1 : 0;
case S_Eb:
if (inst.rm
www.eeworm.com/read/153670/5645545
h dhcp.h
#include "sys.h"
#define DHCP_REFRESH_INTERVAL 3600*4
typedef struct
{
Uint8 opcode;
Uint8 hw_type;
Uint8 hw_addrlen;
Uint8 hop_count;
Uint16 xid_h;
Uint16 xid_l;
Uint1
www.eeworm.com/read/300735/13895574
c uip_arp.c
#include "uip_arp.h"
struct arp_hdr {
struct uip_eth_hdr ethhdr;
u16_t hwtype;
u16_t protocol;
u8_t hwlen;
u8_t protolen;
u16_t opcode;
struct uip_eth_addr shwaddr;
u16_t
www.eeworm.com/read/209211/4982054
c optab.c
#include "l.h"
#define X1 0
#define X2 0
#define X3 0
#define C 0xf200
Optab optab[] =
/* as, fas, srcsp, dstsp, optype, opcode */
{
{ AXXX },
{ AABCD, AXXX, X1, X2, X3, 0x4e71 },
{ AADDB, AXXX,
www.eeworm.com/read/209211/4982444
c optab.c
#include "l.h"
#define X1 0
#define X2 0
#define X3 0
#define C 0xf200
Optab optab[] =
/* as, fas, srcsp, dstsp, optype, opcode */
{
{ AXXX },
{ AABCD, AXXX, X1, X2, X3, 0x4e71 },
{ AADDB, AXXX,
www.eeworm.com/read/349723/3140640
sxnf parameter1.sxnf
LCANET,5
PROG,Synopsys,1997.08,"Created from parameter1.db"
PART,4005epc84-2
SYM,U48,IBUF,SCHNM=IBUF,LIBVER=2.0.0
PIN,O,O,n106,,
PIN,I,I,OPCODE,,
END
SYM,U49,IBUF,SCHNM=IBUF,LIBVER=2.0.0
PIN,O,O,n1
www.eeworm.com/read/18563/794223
v alu.v
//第二章 工程管理与设计输入 第五节 测试激励生成器 例
//Verilog 源代码
//ALU : Arithmetic Logical Unit 算术逻辑运算器
module alu(clk, a, b, opcode, outp_a, outp_s);
input clk;
input [7:0] a, b; //input signal
input [2:0] opc
www.eeworm.com/read/18563/794290
v alu.v
//第二章 工程管理与设计输入 第五节 测试激励生成器 例
//Verilog 源代码
//ALU : Arithmetic Logical Unit 算术逻辑运算器
module alu(clk, a, b, opcode, outp_a, outp_s);
input clk;
input [7:0] a, b; //input signal
input [2:0] opc
www.eeworm.com/read/229812/4750052
inc stkops.inc
; Holes in the opcode space
;===================================================================
s02:
s12:
s22:
s32:
s42:
s62:
s72:
s03:
s13:
s23:
s33:
s53:
s63:
s73:
s65:
s75:
s26:
www.eeworm.com/read/343627/3218917
v alu.v
//第二章 工程管理与设计输入 第五节 测试激励生成器 例
//Verilog 源代码
//ALU : Arithmetic Logical Unit 算术逻辑运算器
module alu(clk, a, b, opcode, outp_a, outp_s);
input clk;
input [7:0] a, b; //input signal
input [2:0] opc