代码搜索：opcode
找到约 2,963 项符合「opcode」的源代码
代码结果 2,963
www.eeworm.com/read/343627/3218387
v alu.v
module alu(clk, a, b, opcode, outp);
input clk;
input [7:0] a, b;
input [2:0] opcode;
output [7:0] outp;
reg [7:0] outp;
always @(posedge clk)
begin
case (opcode) /* synthesis full_c
www.eeworm.com/read/260612/4330061
v alu.v
module alu(clk, a, b, opcode, outp);
input clk;
input [7:0] a, b;
input [2:0] opcode;
output [7:0] outp;
reg [7:0] outp;
always @(posedge clk)
begin
case (opcode) /* synthesis full_c
www.eeworm.com/read/179911/5295385
h miroaci.h
extern int aci_implied_cmd(unsigned char opcode);
extern int aci_write_cmd(unsigned char opcode, unsigned char parameter);
extern int aci_write_cmd_d(unsigned char opcode, unsigned char parameter, uns
www.eeworm.com/read/350097/3130278
h miroaci.h
extern int aci_implied_cmd(unsigned char opcode);
extern int aci_write_cmd(unsigned char opcode, unsigned char parameter);
extern int aci_write_cmd_d(unsigned char opcode, unsigned char parameter, uns
www.eeworm.com/read/131315/5938664
h m88k.h
/* This file has been modified by Data General Corporation, November 1989. */
/*
* Disassembler Instruction Table
*
* The first field of the table is the opcode field. If an opcode
* is specified
www.eeworm.com/read/412483/11198353
txt readme.txt
OPCODE distribution 1.3 (june 2003)
-----------------------
New in Opcode 1.3:
- fixed the divide by 0 bug that was happening when all centers where located on a coordinate axis (than
www.eeworm.com/read/388977/8558967
c obex_connect.c
/*********************************************************************
*
* Filename: obex_connect.c
* Version: 0.9
* Description: Parse and create connect-command.
*
www.eeworm.com/read/387007/8712964
c obex_connect.c
/*********************************************************************
*
* Filename: obex_connect.c
* Version: 0.9
* Description: Parse and create connect-command.
*
www.eeworm.com/read/383287/8957504
v machine.v
//----------------------------------------------------------------------------
module machine( inc_pc, load_acc, load_pc, rd,wr, load_ir,
datactl_ena, halt, clk1, zero, ena, opcode );
output inc
www.eeworm.com/read/379459/9196578
v sm.v
// Copyright Model Technology, a Mentor Graphics
// Corporation company 2003, - All rights reserved.
/*******************************
* Sample solution: - Synthesizable RTL
* - Separate signals,