代码搜索：opcode
找到约 2,963 项符合「opcode」的源代码
代码结果 2,963
www.eeworm.com/read/158872/5591098
h cpu.h
/* CPU family header for i960base.
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
This file is part of the GNU Simulators.
This progr
www.eeworm.com/read/172784/9690697
log sci_alu_comb_misctf_test.log
Host command: C:\PROGRA~1\CDS\TOOLS\BIN\VERILOG.EXE
Command arguments:
sci_alu_comb_misctf_test.v
Verilog_XL_Turbo_NT 2.6.9 log file created Dec 28, 1998 03:37:18
Verilog_XL_Turbo_NT 2.6.9
www.eeworm.com/read/172784/9690727
log sci_alu_comb_calltf_test.log
Host command: C:\PROGRA~1\CDS\TOOLS\BIN\VERILOG.EXE
Command arguments:
sci_alu_comb_calltf_test.v
Verilog_XL_Turbo_NT 2.6.9 log file created Dec 28, 1998 03:28:47
Verilog_XL_Turbo_NT 2.6.9
www.eeworm.com/read/265461/11263480
c cpu_threaded.c
/* gameplaySP
*
* Copyright (C) 2006 Exophase
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
www.eeworm.com/read/104466/15691652
c rpza.c
/*
* Quicktime Video (RPZA) Video Decoder
* Copyright (C) 2003 the ffmpeg project
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser G
www.eeworm.com/read/343627/3218386
xxv alu.xxv
module alu(clk, a, b, opcode, outp);
input clk;
input [7:0] a, b;
input [2:0] opcode;
output [7:0] outp;
reg [7:0] outp;
always @(posedge clk)
begin
casea (opcode) /* synthesis full_
www.eeworm.com/read/18434/788680
v alu.v
module alu(clk, a, b, opcode, outp);
input clk;
input [7:0] a, b;
input [2:0] opcode;
output [7:0] outp;
reg [7:0] outp;
always @(posedge clk)
begin
case (opcode) /* synthesis full_c
www.eeworm.com/read/18434/788740
v alu.v
module alu(clk, a, b, opcode, outp);
input clk;
input [7:0] a, b;
input [2:0] opcode;
output [7:0] outp;
reg [7:0] outp;
always @(posedge clk)
begin
case (opcode) /* synthesis full_c
www.eeworm.com/read/479994/1324872
v alu.v
module alu(clk, a, b, opcode, outp);
input clk;
input [7:0] a, b;
input [2:0] opcode;
output [7:0] outp;
reg [7:0] outp;
always @(posedge clk)
begin
case (opcode) /* synthesis full_c
www.eeworm.com/read/343627/3218186
v alu.v
module alu(clk, a, b, opcode, outp);
input clk;
input [7:0] a, b;
input [2:0] opcode;
output [7:0] outp;
reg [7:0] outp;
always @(posedge clk)
begin
case (opcode) /* synthesis full_c