代码搜索：mult
找到约 6,230 项符合「mult」的源代码
代码结果 6,230
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mult_targets
$description = "The following test creates a makefile to test that a \n "
."rule with multiple targets is equivalent to writing \n"
."many rules, each with one target, and
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msg mult_if.msg
@TM:1137139359
@N: :"":0:0:0:-1|Only System clock will be Autoconstrained
@N: MT195 :"":0:0:0:-1|This timing report estimates place and route data. Please look at the place and route timing report
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tlg mult_if.tlg
Selecting top level module mult_if
@N:"C:\prj\Example-4-10\if_mult\mult_if.v":1:7:1:13|Synthesizing module mult_if
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prf mult_if.prf
#
# Logical Preferences generated for Lucent by Synplify 8.1.0, Build 532R.
#
# Period Constraints
# Output Constraints
# Input Constraints
BLOCK ASYNCPATHS;
# End of generated Logical Pr
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srs mult_if.srs
#
#
#
# Created by Synplify Verilog HDL Compiler version 3.1.0, Build 049R from Synplicity, Inc.
# Copyright 1994-2004 Synplicity, Inc. , All rights reserved.
# Synthesis Netlist written on Fri J
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edn mult_if.edn
(edif mult_if
(edifVersion 2 0 0)
(edifLevel 0)
(keywordMap (keywordLevel 0))
(status
(written
(timeStamp 2006 1 13 16 3 3)
(author "Synplicity, Inc.")
(program "
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srr mult_if.srr
#Program: Synplify Pro 8.1
#OS: Windows_NT
$ Start of Compile
#Fri Jan 13 16:03:02 2006
Synplicity Verilog Compiler, version 3.1.0, Build 049R, built May 3 2005
Copyright (C) 1994-2005, Synp
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srm mult_if.srm
f "noname"; #file 0
f "noname"; #file 1
f "c:\eda\synplicity\fpga_81\lib\lucent\ec.v"; #file 2
f "c:\prj\example-4-10\if_mult\mult_if.v"; #file 3
VNAME 'LUCENT.VLO.PRIM'; # view id 0
VNAME 'LUCEN
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prf mult_if.prf
BLOCK ASYNCPATHS ;
BLOCK RESETPATHS ;
BLOCK RD_DURING_WR_PATHS ;
BLOCK INTERCLOCKDOMAIN PATHS;