代码搜索:mult
找到约 6,230 项符合「mult」的源代码
代码结果 6,230
www.eeworm.com/read/269205/4246888
srr mult_if.srr
#Program: Synplify Pro 8.1
#OS: Windows_NT
$ Start of Compile
#Fri Jan 13 16:03:02 2006
Synplicity Verilog Compiler, version 3.1.0, Build 049R, built May 3 2005
Copyright (C) 1994-2005, Synp
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srm mult_if.srm
f "noname"; #file 0
f "noname"; #file 1
f "c:\eda\synplicity\fpga_81\lib\lucent\ec.v"; #file 2
f "c:\prj\example-4-10\if_mult\mult_if.v"; #file 3
VNAME 'LUCENT.VLO.PRIM'; # view id 0
VNAME 'LUCEN
www.eeworm.com/read/269205/4246890
prd if_mult.prd
#-- Synplicity, Inc.
#-- Version Synplify Pro 8.1
#-- Project file C:\prj\Example-4-10\if_mult\SynplifyPro\if_mult.prd
#-- Written on Fri Jan 13 16:03:02 2006
#
### Watch Implementation type ##
www.eeworm.com/read/269205/4246899
prf mult_if.prf
BLOCK ASYNCPATHS ;
BLOCK RESETPATHS ;
BLOCK RD_DURING_WR_PATHS ;
BLOCK INTERCLOCKDOMAIN PATHS;
www.eeworm.com/read/269205/4246906
edf mult_if.edf
(edif mult_if
(edifVersion 2 0 0)
(edifLevel 0)
(keywordMap (keywordLevel 0))
(status
(written
(timestamp 2006 01 16 01 41 36)
(program "Precision RTL Synthesis" (version "2005a.
www.eeworm.com/read/269205/4246907
psp if_mult.psp
#
#
# Precision RTL Synthesis 2005a.56OEM_Lattice (Production Release) Tue May 24 01:00:50 PDT 2005
#
# Copyright (c) Mentor Graphics Corporation, 1996-2005, All Rights Reserved.
# Po
www.eeworm.com/read/268796/4249962
mult_rules
# -*-perl-*-
#$Id: mult_rules,v 1.2 2005/12/18 02:05:45 rockyb Exp $
$description = "\
The following test creates a makefile to test
www.eeworm.com/read/268796/4249968
mult_targets
$description = "The following test creates a makefile to test that a \n "
."rule with multiple targets is equivalent to writing \n"
."many rules, each with one target, and
www.eeworm.com/read/442451/1761717
xco mult.xco
# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = D:\work\ISE\c6
SET speedgrade = -12
SET simulationfiles = Behavioral
SET asysymb
www.eeworm.com/read/442451/1761725
xco mult.xco
# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = D:\work\ISE\c6
SET speedgrade = -12
SET simulationfiles = Behavioral
SET asysymb