代码搜索：maxII
找到约 205 项符合「maxII」的源代码
代码结果 205
www.eeworm.com/read/469746/6926094
tdf cntr_qv7.tdf
--lpm_counter DEVICE_FAMILY="MAX II" lpm_direction="UP" lpm_width=4 clk_en clock cnt_en q
--VERSION_BEGIN 4.2 cbx_cycloneii 2004:08:25:19:39:42:SJ cbx_lpm_add_sub 2004:10:25:10:56:48:SJ cbx_lpm_compa
www.eeworm.com/read/443501/7631650
txt readme.txt
资料说明
------------------------------------------------
1.文件
- FT245 相关驱动及烧写文件
- 原理图
- 印制电路板
- EPM240T100C5 烧写文件
------------------------------------------------
www.eeworm.com/read/326319/13147622
tdf cntr_np7.tdf
--lpm_counter DEVICE_FAMILY="MAX II" lpm_direction="UP" lpm_width=4 clk_en clock q sclr
--VERSION_BEGIN 4.1 cbx_cycloneii 2004:05:18:11:27:16:SJ cbx_lpm_add_sub 2004:06:23:12:24:04:SJ cbx_lpm_compare
www.eeworm.com/read/326319/13148008
tdf cntr_np7.tdf
--lpm_counter DEVICE_FAMILY="MAX II" lpm_direction="UP" lpm_width=4 clk_en clock q sclr
--VERSION_BEGIN 4.1 cbx_cycloneii 2004:05:18:11:27:16:SJ cbx_lpm_add_sub 2004:06:23:12:24:04:SJ cbx_lpm_compare
www.eeworm.com/read/152166/12135073
tdf cntr_p47.tdf
--lpm_counter DEVICE_FAMILY="MAX II" lpm_direction="UP" lpm_width=4 aclr clock q
--VERSION_BEGIN 4.2 cbx_cycloneii 2004:08:25:19:39:42:SJ cbx_lpm_add_sub 2004:10:25:10:56:48:SJ cbx_lpm_compare 2004:1
www.eeworm.com/read/161013/5564363
tdf cntr_np7.tdf
--lpm_counter DEVICE_FAMILY="MAX II" lpm_direction="UP" lpm_width=4 clk_en clock q sclr
--VERSION_BEGIN 4.1 cbx_cycloneii 2004:05:18:11:27:16:SJ cbx_lpm_add_sub 2004:06:23:12:24:04:SJ cbx_lpm_compare
www.eeworm.com/read/327878/6299987
v altufm_osc0.v
// megafunction wizard: %MAX II oscillator%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altufm_osc
// ============================================================
// File Name: altufm
www.eeworm.com/read/217144/4876026
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity maxii_and1 is
port(
Y : out vl_logic;
IN1 : in vl_logic
);
end maxii_and1;
www.eeworm.com/read/208358/4993595
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity maxii_and1 is
port(
Y : out vl_logic;
IN1 : in vl_logic
);
end maxii_and1;
www.eeworm.com/read/268991/4247982
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity maxii_and1 is
port(
Y : out vl_logic;
IN1 : in vl_logic
);
end maxii_and1;