代码搜索：interconnect
找到约 755 项符合「interconnect」的源代码
代码结果 755
www.eeworm.com/read/451829/7455189
vhd spi_master.vhd
-- File: spi_master.vhd
--
-- Created: 12-12-02 JRH
-- This file contains the interconnect structure of the SPI interface to the
-- uC interface. This is the top level file for the SIP M
www.eeworm.com/read/400975/11566423
vhd spi_master.vhd
-- File: spi_master.vhd
--
-- Created: 12-12-02 JRH
-- This file contains the interconnect structure of the SPI interface to the
-- uC interface. This is the top level file for the SIP M
www.eeworm.com/read/7866/137509
vhd spi_master.vhd
-- File: spi_master.vhd
--
-- Created: 12-12-02 JRH
-- This file contains the interconnect structure of the SPI interface to the
-- uC interface. This is the top level file for the SIP M
www.eeworm.com/read/316872/3595764
kconfig
#
# wan devices configuration
#
menuconfig WAN
bool "Wan interfaces support"
---help---
Wide Area Networks (WANs), such as X.25, Frame Relay and leased
lines, are used to interconnect Local A
www.eeworm.com/read/16802/692287
log,1 signoise.log,1
INFO: Finished loading SigNoise device libraries
INFO: Using working device library 'E:/class_cadence/Minisystem/devices.dml'
INFO: Loaded existing Interconnect file 'E:/class_cadence/Minisystem/int
www.eeworm.com/read/22036/840832
log,1 signoise.log,1
INFO: Finished loading SigNoise device libraries
INFO: Using working device library 'E:/class_cadence/Minisystem/devices.dml'
INFO: Loaded existing Interconnect file 'E:/class_cadence/Minisystem/int
www.eeworm.com/read/39742/1135448
log,1 signoise.log,1
INFO: Finished loading SigNoise device libraries
INFO: Using working device library 'E:/class_cadence/Minisystem/devices.dml'
INFO: Loaded existing Interconnect file 'E:/class_cadence/Minisystem/int
www.eeworm.com/read/21695/838875
log,3 signoise.log,3
WARNING: There are no voltage nets defined in this design.
INFO: Using default signal_icnlibs = [interconn.iml cds_interconn.iml *.iml]
INFO: Loaded existing Interconnect file 'E:/Cadence/PCB图的导入、放置
www.eeworm.com/read/39074/1119711
log,3 signoise.log,3
WARNING: There are no voltage nets defined in this design.
INFO: Using default signal_icnlibs = [interconn.iml cds_interconn.iml *.iml]
INFO: Loaded existing Interconnect file 'E:/Cadence/PCB图的导入、放置
www.eeworm.com/read/316872/3592728
makefile
#
# Makefile for RapidIO interconnect services
#
obj-y += rio.o rio-access.o rio-driver.o rio-scan.o rio-sysfs.o
obj-$(CONFIG_RAPIDIO) += switches/