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找到约 10,000 项符合「fpga」的源代码

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www.eeworm.com/read/345690/11795161

txt 雙2－4譯碼器：74139.txt

-- Dual 2-to-4 Decoder -- A set of conditional signal assignments model a dual 2-to-4 decoder -- uses 1993 std VHDL -- download from: www.pld.com.cn & www.fpga.com.cn library IEEE; use IEEE.Std
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www.eeworm.com/read/345690/11795195

txt 經典雙進程狀態機(含test beach).txt

-- Classic 2-Process State Machine and Test Bench -- MEALY TYPE STATE MACHINE EXAMPLE -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; ENTITY fsm I
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www.eeworm.com/read/152519/12108243

txt state_classic经典双进程状态机.txt

-- Classic 2-Process State Machine and Test Bench -- MEALY TYPE STATE MACHINE EXAMPLE -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; ENTITY fsm I
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www.eeworm.com/read/338786/12283569

c idetest.c

#include "..\header\armperipherals.h" #include "..\header\FPGA_peripherals.h" #include #include "omap30.h" #include "omap30_arminth.h" #include "omap1510_inth2.h" #include "swi.h"
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www.eeworm.com/read/338782/12283602

c ts.c

#include "..\header\armperipherals.h" #include "..\header\FPGA_peripherals.h" #include "omap30.h" #include "omap30_arminth.h" #include "omap1510_inth2.h" #define BCS 0x04 #define BCLK
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www.eeworm.com/read/149607/12362857

txt state_areset.txt

-- State Machine with Asynchronous Reset -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; entity stmch1 is port(clk, in1, rst: in std_logic;
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www.eeworm.com/read/149607/12362866

txt register_374.txt

-- Octal D-Type Register with 3-State Outputs -- Simple model of an Octal D-type register with three-state outputs using two concurrent statements. -- download from: www.fpga.com.cn & www.pld.com.cn
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www.eeworm.com/read/149607/12362876

txt shift_register_164.txt

-- TTL164 Shift Register -- download from: www.fpga.com.cn & www.pld.com.cn library IEEE; use IEEE.Std_logic_1164.all; ENTITY dev164 IS PORT(a, b, nclr, clock : IN BIT; q : BUFFE
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www.eeworm.com/read/149607/12362967

txt decoder_hct139.txt

-- Dual 2-to-4 Decoder -- A set of conditional signal assignments model a dual 2-to-4 decoder -- uses 1993 std VHDL -- download from: www.pld.com.cn & www.fpga.com.cn library IEEE; use IEEE.Std
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www.eeworm.com/read/149607/12362975

txt state_classic.txt

-- Classic 2-Process State Machine and Test Bench -- MEALY TYPE STATE MACHINE EXAMPLE -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; ENTITY fsm I
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