代码搜索:fpga

找到约 10,000 项符合「fpga」的源代码

代码结果 10,000
www.eeworm.com/read/390924/8433417

txt 經典雙進程狀態機(含test beach).txt

-- Classic 2-Process State Machine and Test Bench -- MEALY TYPE STATE MACHINE EXAMPLE -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; ENTITY fsm I
www.eeworm.com/read/433021/8551825

vhd 双2-4译码器_74139.vhd

-- Dual 2-to-4 Decoder -- A set of conditional signal assignments model a dual 2-to-4 decoder -- uses 1993 std VHDL -- download from: www.pld.com.cn & www.fpga.com.cn library IEEE; use IEEE.Std
www.eeworm.com/read/288602/8619570

txt vhdl.txt

-- Classic 2-Process State Machine and Test Bench -- MEALY TYPE STATE MACHINE EXAMPLE -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; ENTITY fsm I
www.eeworm.com/read/384241/8887978

c com.c

// RS-232 example // Compiles with Microsoft Visual C++ 5.0/6.0 // (c) fpga4fun.com KNJN LLC - 2003, 2004, 2005, 2006 #include #include #include HANDLE hCom;
www.eeworm.com/read/284640/8912178

txt 经典双进程状态机(含test beach).txt

-- Classic 2-Process State Machine and Test Bench -- MEALY TYPE STATE MACHINE EXAMPLE -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; ENTITY fsm I
www.eeworm.com/read/379647/9190680

txt 带同步复位的状态机.txt

-- State Machine with Asynchronous Reset -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; entity stmch1 is port(clk, in1, rst: in std_logic;
www.eeworm.com/read/379647/9190691

txt 带三态输出的8位d寄存器:74374.txt

-- Octal D-Type Register with 3-State Outputs -- Simple model of an Octal D-type register with three-state outputs using two concurrent statements. -- download from: www.fpga.com.cn & www.pld.com.cn
www.eeworm.com/read/169233/9873580

frm 主窗口.frm

VERSION 5.00 Object = "{648A5603-2C6E-101B-82B6-000000000014}#1.1#0"; "MSCOMM32.OCX" Begin VB.Form 主窗口 Caption = "FPGA串行通讯" ClientHeight = 5745 ClientLeft = -1620
www.eeworm.com/read/166954/9988199

txt 移位寄存器:74164.txt

-- TTL164 Shift Register -- download from: www.fpga.com.cn & www.pld.com.cn library IEEE; use IEEE.Std_logic_1164.all; ENTITY dev164 IS PORT(a, b, nclr, clock : IN BIT; q : BUFFE
www.eeworm.com/read/166954/9988221

txt 经典双进程状态机(含test beach).txt

-- Classic 2-Process State Machine and Test Bench -- MEALY TYPE STATE MACHINE EXAMPLE -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; ENTITY fsm I