代码搜索:fpga

找到约 10,000 项符合「fpga」的源代码

代码结果 10,000
www.eeworm.com/read/164962/10080404

txt counter_nbit.txt

-- n-Bit Synchronous Counter -- dowload from: www.fpga.com.cn & www.pld.com.cn LIBRARY ieee; USE ieee.Std_logic_1164.ALL; USE ieee.Std_logic_unsigned.ALL; ENTITY cntrnbit IS GENERIC(
www.eeworm.com/read/163129/10174670

v 相应加法器的测试向量(test bench).v

// download from: www.pld.com.cn & www.fpga.com.cn module test_counter; reg clk, rst; wire [7:0] count; counter #(5,10) dut (count,clk,rst); initial // Clock generator begin cl
www.eeworm.com/read/353811/10416312

txt 多路选择器(使用when-else语句).txt

-- Multiplexer 16-to-4 using if-then-elsif-else Statement -- download from www.pld.com.cn & www.fpga.com.cn library ieee; use ieee.std_logic_1164.all; entity mux is port( a, b, c, d:
www.eeworm.com/read/353811/10416448

txt 三态总线(注2).txt

VHDL:Tri-State Buses download from: http://www.fpga.com.cn prebus.vhd LIBRARY IEEE; USE ieee.std_logic_1164.ALL; ENTITY prebus IS PORT( my_in : IN STD_LOGIC_VECTOR(7 D
www.eeworm.com/read/276507/10733443

srr dds.srr

#Build: Synplify Pro 8.6.2, Build 013R, Jun 5 2006 #install: C:\Program Files\Synplicity\fpga_862 #OS: Windows XP 5.1 #Hostname: DONNYLU #Wed Oct 31 14:45:37 2007 $ Start of Compile #Wed Oc
www.eeworm.com/read/417397/10991764

txt 计数器:generic语句的应用.txt

-- n-Bit Synchronous Counter -- dowload from: www.fpga.com.cn & www.pld.com.cn LIBRARY ieee; USE ieee.Std_logic_1164.ALL; USE ieee.Std_logic_unsigned.ALL; ENTITY cntrnbit IS GENERIC(
www.eeworm.com/read/417397/10991814

txt 多路选择器(使用when-else语句).txt

-- Multiplexer 16-to-4 using if-then-elsif-else Statement -- download from www.pld.com.cn & www.fpga.com.cn library ieee; use ieee.std_logic_1164.all; entity mux is port( a, b, c, d:
www.eeworm.com/read/417397/10991816

txt 多路选择器(使用if-else语句).txt

-- Multiplexer 16-to-4 using if-then-elsif-else Statement -- download from www.pld.com.cn & www.fpga.com.cn library ieee; use ieee.std_logic_1164.all; entity mux is port( a, b, c, d:
www.eeworm.com/read/417397/10991818

txt 多路选择器(使用select语句).txt

-- Multiplexer 16-to-4 using if-then-elsif-else Statement -- download from www.pld.com.cn & www.fpga.com.cn library ieee; use ieee.std_logic_1164.all; entity mux is port( a, b, c, d:
www.eeworm.com/read/417397/10991819

txt 8位总线收发器.txt

-- Multiplexer 16-to-4 using if-then-elsif-else Statement -- download from www.pld.com.cn & www.fpga.com.cn library ieee; use ieee.std_logic_1164.all; entity mux is port( a, b, c, d: