代码搜索：fpga

找到约 10,000 项符合「fpga」的源代码

代码结果 10,000
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/415351/11075467

vhd 一个简单的状态机.vhd

-- MAX+plus II VHDL Example -- State Machine -- Copyright (c) 1994 Altera Corporation -- download from: www.pld.com.cn & www.fpga.com.cn Library IEEE ; use IEEE.std_logic_1164.all ; ENTIT
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www.eeworm.com/read/415351/11075519

vhd 带load、clr等功能的寄存器.vhd

-- Register Inference -- Download from: http://www.fpga.com.cn Library IEEE ; use IEEE.std_logic_1164.all ; ENTITY reginf IS PORT ( d, clk, clr, pre, load, data : IN BIT; q1, q2,
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www.eeworm.com/read/415351/11075539

v 加法器源程序.v

// download from: www.pld.com.cn & www.fpga.com.cn module counter (count, clk, reset); output [7:0] count; input clk, reset; reg [7:0] count; parameter tpd_clk_to_count = 1; parameter
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www.eeworm.com/read/415351/11075594

vhd 带load、clr等功能的寄存器.vhd

-- Register Inference -- Download from: http://www.fpga.com.cn Library IEEE ; use IEEE.std_logic_1164.all ; ENTITY reginf IS PORT ( d, clk, clr, pre, load, data : IN BIT; q1, q2,
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www.eeworm.com/read/415351/11075609

v 加法器源程序.v

// download from: www.pld.com.cn & www.fpga.com.cn module counter (count, clk, reset); output [7:0] count; input clk, reset; reg [7:0] count; parameter tpd_clk_to_count = 1; parameter
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www.eeworm.com/read/268989/11112296

v 计数器.v

// Efficient Counter Inference // download from: www.pld.com.cn & www.fpga.com.cn module counters (d, clk, clear, ld, enable, up_down, qa, qb, qc, qd, qe, qf, qg, qh, qi, qj,
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www.eeworm.com/read/268031/11156137

txt 最高优先级编码器.txt

-- Highest Priority Encoder -- download from www.pld.com.cn & www.fpga.com.cn LIBRARY ieee; USE ieee.std_logic_1164.ALL; entity priority is port(I : in bit_vector(7 downto 0); --input
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www.eeworm.com/read/436490/7769241

_info

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www.eeworm.com/read/291453/8417527

txt 多路选择器（使用when－else语句）.txt

-- Multiplexer 16-to-4 using if-then-elsif-else Statement -- download from www.pld.com.cn & www.fpga.com.cn library ieee; use ieee.std_logic_1164.all; entity mux is port( a, b, c, d:
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www.eeworm.com/read/291453/8417576

txt 三态总线（注2）.txt

VHDL:Tri-State Buses download from: http://www.fpga.com.cn prebus.vhd LIBRARY IEEE; USE ieee.std_logic_1164.ALL; ENTITY prebus IS PORT( my_in : IN STD_LOGIC_VECTOR(7 D
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