代码搜索：fpga
找到约 10,000 项符合「fpga」的源代码
代码结果 10,000
www.eeworm.com/read/145313/12736096
txt 最高优先级编码器.txt
-- Highest Priority Encoder
-- download from www.pld.com.cn & www.fpga.com.cn
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
entity priority is
port(I : in bit_vector(7 downto 0); --input
www.eeworm.com/read/145313/12736097
vhd 各种功能的计数器.vhd
-- MAX+plus II VHDL Example
-- Efficient Counter Inference
-- Copyright (c) 1994 Altera Corporation
-- download from:www.pld.com.cn & www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all
www.eeworm.com/read/145313/12736100
vhd 一个简单的状态机.vhd
-- MAX+plus II VHDL Example
-- State Machine
-- Copyright (c) 1994 Altera Corporation
-- download from: www.pld.com.cn & www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTIT
www.eeworm.com/read/145313/12736169
vhd 带load、clr等功能的寄存器.vhd
-- Register Inference
-- Download from: http://www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY reginf IS
PORT
(
d, clk, clr, pre, load, data : IN BIT;
q1, q2,
www.eeworm.com/read/145313/12736195
v 加法器源程序.v
// download from: www.pld.com.cn & www.fpga.com.cn
module counter (count, clk, reset);
output [7:0] count;
input clk, reset;
reg [7:0] count;
parameter tpd_clk_to_count = 1;
parameter
www.eeworm.com/read/246188/12752043
+
-- n-bit Adder using the Generate Statement
-- download from: www.fpga.com.cn & www.pld.com.cn
library IEEE;
use IEEE.Std_logic_1164.all;
ENTITY addn IS
GENERIC(n : POSITIVE := 3); --no.
www.eeworm.com/read/246188/12752122
ί
-- Highest Priority Encoder
-- download from www.pld.com.cn & www.fpga.com.cn
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
entity priority is
port(I : in bit_vector(7 downto 0); --input
www.eeworm.com/read/145129/12752248
txt 最高优先级编码器.txt
-- Highest Priority Encoder
-- download from www.pld.com.cn & www.fpga.com.cn
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
entity priority is
port(I : in bit_vector(7 downto 0); --input
www.eeworm.com/read/145129/12752253
vhd 各种功能的计数器.vhd
-- MAX+plus II VHDL Example
-- Efficient Counter Inference
-- Copyright (c) 1994 Altera Corporation
-- download from:www.pld.com.cn & www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all
www.eeworm.com/read/145129/12752255
vhd 一个简单的状态机.vhd
-- MAX+plus II VHDL Example
-- State Machine
-- Copyright (c) 1994 Altera Corporation
-- download from: www.pld.com.cn & www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTIT