代码搜索：flw
找到约 95 项符合「flw」的源代码
代码结果 95
www.eeworm.com/read/392017/8367243
flw modl.flw
*Lth order pure differentiation delta-sigma
in 10 H^L
10 out 1
out in -1
.pre syms z L
.pre H=1/(z-1);
*.pre k=1;
.tf in out
.tf out out
*.post z=tf('z',1);
www.eeworm.com/read/392017/8367246
flw crfbnum.flw
*3rd order CRFB delta-sigma
in 10 b1
in 20 b2
in 30 b3
in 40 b4
10 20 1/(z-1)
20 30 1*z/(z-1)
30 40 1/(z-1)
40 out k
out 10 -a1
out 20 -a2
out 30 -a3
40 20 -g1
*initialization
.pre sym
www.eeworm.com/read/392017/8367249
flw efb.flw
*error feedback delta sigma
in 10 1 * comments
10 out 1 * can
10 20 1 * now
out 20 -1 * be added to
20 in F * the end of line
.pre syms z * initials
*NTF=1-F;
.pre F=2/z-z^-
www.eeworm.com/read/392017/8367251
flw crfbsym.flw
*3rd order symbolic CRFB delta-sigma
* symbolic parameters, numeric k
in 10 b1
in 20 b2
in 30 b3
in 40 b4
10 20 1/(z-1)
20 30 1*z/(z-1)
30 40 1/(z-1)
40 out k
out 10 -a1
out 20 -a2
out 30
www.eeworm.com/read/392017/8367253
flw integra.flw
*delayed integrator
*0 1 1
1 2 z^(-1)
2 1 1
.pre syms z
.tf 1 2
*backwards it is delayless
.tf 2 1
.post z=tf('z',1);
www.eeworm.com/read/392017/8367255
flw zpar.flw
*circuit defined as 2-port z-parameters
*is terminated by impedances ZS and ZL.
*Vin is the voltage of the source.
*v2 is the output voltage of 2-port.
vin i1 1/(ZS+z11)
i1 i2 -z21/(z22+ZL)
i2
www.eeworm.com/read/392017/8367259
flw iir.flw
* IIR filter, see manual.pdf
in out 1
in FF1 z^(-1)
FF1 FF2 z^(-1)
FF1 out a
FF2 out b
out FB1 z^(-1)
FB1 FB2 z^(-1)
FB1 out -c
FB2 out -d
.pre syms z a b c d
.tf in out
www.eeworm.com/read/392017/8367261
flw fiori.flw
* A third order DeltaSigma. From paper by Fiori&Maloberti at ecctd2005
in 10 1
10 20 z^(-1)
20 10 3
20 10 -3*z^(-1)
20 10 z^(-2)
20 noi k
noi out 1
out dac (3-3*z^(-1)+z^(-2))
dac in -1
.pre
www.eeworm.com/read/392017/8367263
flw biquad.flw
* Biquad filter
in 1 g3
1 2 H1
2 3 H2
2 1 g1
3 1 g4
3 1 s*c4
.pre syms s g3 c1 a g4 g1 c4
.pre H1=-1/(s*c1);
.pre H2=a/s;
.tf in 3
www.eeworm.com/read/17583/740099
flw fpga.flw
####################################################
## FileName: fpga.flw
##
## Flow File to run Xilinx FPGA Flow
##
## Version: 6.1.1
## $Header: /devl/xcs/repo/env/Jobs/Xflow/data/flowfiles/fpga.fl