代码搜索：dds

找到约 10,000 项符合「dds」的源代码

代码结果 10,000
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/350827/10707216

eww dds.eww

$WS_DIR$\dds.ewp
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www.eeworm.com/read/350827/10707219

ewp dds.ewp

1 Debug MSP430
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www.eeworm.com/read/350827/10707233

ewd dds.ewd

1 Debug MSP430
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www.eeworm.com/read/350827/10707246

dep dds.dep

2 Debug $PROJ_DIR$\MSP430-fw-hamtables.h
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www.eeworm.com/read/350569/10731925

dds9852

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www.eeworm.com/read/158730/10731984

c dds.c

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www.eeworm.com/read/276507/10733394

prj dds.prj

#-- Synplicity, Inc. #-- Version Synplify Pro 8.6.2 #-- Project file D:\Work\dds_20071031\dds.prj #-- Written on Wed Oct 31 14:10:19 2007 #add_file options add_file -verilog "dds.v" #imp
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www.eeworm.com/read/276507/10733401

v dds.v

module dds(clk, reset, k, initial_phase, data_out ); input clk, reset; input[9:0] k, initial_phase; output[7:0] data_out; // Addr
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www.eeworm.com/read/276507/10733402

prd dds.prd

#-- Synplicity, Inc. #-- Version Synplify Pro 8.6.2 #-- Project file D:\Work\dds_20071031\dds.prd #-- Written on Wed Oct 31 14:10:19 2007 # ### Watch Implementation type ### # watch_impl -all
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www.eeworm.com/read/276507/10733408

srd dds.srd

f "noname"; #file 0 f "c:\program files\synplicity\fpga_862\lib\proasic\proasic.v"; #file 1 f "d:\work\dds_20071031\dds.v"; #file 2 VNAME 'work.dds.verilog'; # view id 0 @EuyRsFCDN88CRsbN0HRDLssNH
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