代码搜索:dataIn

找到约 2,888 项符合「dataIn」的源代码

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v eth_register.v

`include "timescale.v" module eth_register(DataIn, DataOut, Write, Clk, Reset, SyncReset); parameter WIDTH = 8; // default parameter of the register width parameter RESET_VALUE = 0; in
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v test_txsystem.v

`timescale 1ns / 1ps module test_txsystem_v; // Inputs reg clock; reg reset; reg odd_noteven; reg write; reg [7:0] datain; // Outputs wire busy; wire txdata; // Instantiat
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v test_txsysrtl.v

`timescale 1ns / 1ps module test_TXSysRTL_v; // Inputs reg clock; reg reset; reg odd_noteven; reg write; reg [7:0] Datain; // Outputs wire Busy; wire TxData; //test data array reg [
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asm chr1335.asm

;********************CHR1335******************** ;本程序实现液晶显示控制器SED1335的字符和汉字显示。 ;入口参数:汉字左上角的X坐标在SOU中,Y坐标在SOUH中。 ;出口参数:无。 ;占用资源:W,STATUS,RB0~RB2,RC,023H,024H,025H,028H,029H,二重堆栈。 ;说 明:1.显示屏为320*
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m symbol_syn.m

clear; load c; Fs=38400; %WCDMA信号的采样率 nsamp=16; %过采样率 delay=3; %根号下升余弦的群时延 datain=c; %这里c为WCDMA系统的扰码数据 Num=length(datain); %计算相关的长度 dataout=RRCsend(datain,Fs,nsamp,delay); %调用子程序
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vhd ad.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity ad is port(busy:in std_logic; datain:in unsigned(7 downto 0); clk:in std_logic; dataout:out unsigned
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vhd ad.vhd

--AD library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity ad is port(busy:in std_logic; datain:in unsigned(7 downto 0); clk:in std_logic; dataout:out un
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h t2.h

/* This is a test for maxidx: rand */ #define NX 16 #define FNAME "t2" #define MAXERROR 0 #pragma DATA_SECTION (x,".datain") DATA x[NX] ={ 29499, -17621, 7002, -919, 25644, 17176, -2853,
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txt 6.3.5快速排序.txt

DATS EQU 20H N EQU 5DH QUEUE EQU 1FH F DATA 3CH R DATA 3DH TST: MOV DPTR,#LIST MOV P2,#DATS MOV R0,#0 MOV R2,#N CPY: CLR A MOVC A,@A+DPTR MOVX @R0,A INC DPTR
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v sdr_data_path.v

module sdr_data_path( CLK, RESET_N, DATAIN, DM, DQOUT, DQM ); `include "Sdram_Params.h" input CLK;