代码搜索：dataIn
找到约 2,888 项符合「dataIn」的源代码
代码结果 2,888
www.eeworm.com/read/387425/8683675
v eth_registers.v
`include "eth_defines.v"
`include "timescale.v"
module eth_registers( DataIn, Address, Rw, Cs, Clk, Reset, DataOut,
r_RecSmall, r_Pad, r_HugEn, r_CrcEn, r_DlyCrcEn,
www.eeworm.com/read/387425/8683684
v eth_register.v
`include "timescale.v"
module eth_register(DataIn, DataOut, Write, Clk, Reset, SyncReset);
parameter WIDTH = 8; // default parameter of the register width
parameter RESET_VALUE = 0;
in
www.eeworm.com/read/429594/8800933
txt 6.3.5快速排序.txt
DATS EQU 20H
N EQU 5DH
QUEUE EQU 1FH
F DATA 3CH
R DATA 3DH
TST:
MOV DPTR,#LIST
MOV P2,#DATS
MOV R0,#0
MOV R2,#N
CPY:
CLR A
MOVC A,@A+DPTR
MOVX @R0,A
INC DPTR
www.eeworm.com/read/285298/8852475
txt 6.3.5快速排序.txt
DATS EQU 20H
N EQU 5DH
QUEUE EQU 1FH
F DATA 3CH
R DATA 3DH
TST:
MOV DPTR,#LIST
MOV P2,#DATS
MOV R0,#0
MOV R2,#N
CPY:
CLR A
MOVC A,@A+DPTR
MOVX @R0,A
INC DPTR
www.eeworm.com/read/428596/8856722
v sdr_data_path.v
module sdr_data_path(
CLK,
RESET_N,
DATAIN,
DM,
DQOUT,
DQM
);
`include "Sdram_Params.h"
input CLK;
www.eeworm.com/read/427429/8945560
v sdr_data_path.v
module sdr_data_path(
CLK,
RESET_N,
DATAIN,
DM,
DQOUT,
DQM
);
`include "Sdram_Params.h"
input CLK;
www.eeworm.com/read/426736/9002692
vhd ad.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity ad is
port(busy:in std_logic;
datain:in unsigned(7 downto 0);
clk:in std_logic;
dataout:out unsigned
www.eeworm.com/read/185603/9026023
hier_info test.hier_info
|TEST
MOSI SPI:inst.CLK
GCLK => counter25:inst5.clock
WR => SPI:inst.WR
RD => SPI:inst.RD
RD => INTERFACE:inst1.RD
MIMO => SPI:inst.MISO
MIMO => T_MISO.DATAIN
RESET2
www.eeworm.com/read/381044/9113332
vhd ad.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity ad is
port(busy:in std_logic;
datain:in unsigned(7 downto 0);
clk:in std_logic;
dataout:out unsigned
www.eeworm.com/read/381044/9113650
vhd ad.vhd
--AD
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity ad is
port(busy:in std_logic;
datain:in unsigned(7 downto 0);
clk:in std_logic;
dataout:out un