代码搜索：dataIn
找到约 2,888 项符合「dataIn」的源代码
代码结果 2,888
www.eeworm.com/read/343298/11959542
asv de_bit_interleaver.asv
function [out]=de_bit_interleaver(datain,length,rate);
if(isequal(rate,[0 0 0 0 0]))
Ntds=2;
Ncbps=100;
Ntint=10;
Ncyc=33;
Ncbp6s=300;
Nibp6s=100;
elseif(isequal(rate,[
www.eeworm.com/read/343298/11959641
m bit_interleaver.m
function [out]=Bit_interleaver(datain,length,rate);
if (isequal(rate,[0 0 0 0 0]))
Ntds=2;
Ncbps=100;
Ntint=10;
Ncyc=33;
Ncbp6s=300;
Nibp6s=100;
elseif(isequal(rate,[0
www.eeworm.com/read/343298/11959678
m de_bit_interleaver.m
function [out]=de_bit_interleaver(datain,length,rate);
if(isequal(rate,[0 0 0 0 0]))
Ntds=2;
Ncbps=100;
Ntint=10;
Ncyc=33;
Ncbp6s=300;
Nibp6s=100;
elseif(isequal(rate,[
www.eeworm.com/read/343138/11969972
vhd keyboard.vhd
library ieee;
use ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity Keyboard is
port (
datain, clkin : in std_logic ; -- PS2 clk and data
fclk,
www.eeworm.com/read/211745/15174690
vhd fifo.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fifo is
port( DataIn :in std_logic_vector(7 downto 0);
DataOut :out std_logic_vector(7 downto 0);
clk
www.eeworm.com/read/14792/410922
vhd fifo.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fifo is
port( DataIn :in std_logic_vector(7 downto 0);
DataOut :out std_logic_vector(7 downto 0);
clk
www.eeworm.com/read/17540/737628
cpld
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fifo is
port( DataIn :in std_logic_vector(7 downto 0);
DataOut :out std_logic_vector(7 downto 0);
clk
www.eeworm.com/read/17609/742791
vhd fifo.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fifo is
port( DataIn :in std_logic_vector(7 downto 0);
DataOut :out std_logic_vector(7 downto 0);
clk
www.eeworm.com/read/17895/766374
vhd fifo.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fifo is
port( DataIn :in std_logic_vector(7 downto 0);
DataOut :out std_logic_vector(7 downto 0);
clk
www.eeworm.com/read/17921/767351
vhd fifo.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fifo is
port( DataIn :in std_logic_vector(7 downto 0);
DataOut :out std_logic_vector(7 downto 0);
clk