代码搜索：dataIn
找到约 2,888 项符合「dataIn」的源代码
代码结果 2,888
www.eeworm.com/read/18488/791209
vhd ad.vhd
--AD
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity ad is
port(busy:in std_logic;
datain:in unsigned(7 downto 0);
clk:in std_logic;
dataout:out un
www.eeworm.com/read/18488/791286
vhd counter_1024.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter_1024 is
port(clk,clr,en,updn,bcdwr:in std_logic;
datain:in std_logic_vector(9 downt
www.eeworm.com/read/18616/797463
vhd counter_1024.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter_1024 is
port(clk,clr,en,updn,bcdwr:in std_logic;
datain:in std_logic_vector(9 downt
www.eeworm.com/read/479516/1331453
hier_info debounce.hier_info
|Debounce
key => temp1.DATAIN
clk => key_out~1.IN0
clk => temp2.CLK
clk => temp1.CLK
key_out
www.eeworm.com/read/476527/1368482
hier_info control.hier_info
|control
clk => sstart.CLK
clk => count[0].CLK
clk => count[1].CLK
clk => count[2].CLK
clk => count[3].CLK
start => sstart.DATAIN
startstop
www.eeworm.com/read/296366/3904390
vhd ad.vhd
--AD
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity ad is
port(busy:in std_logic;
datain:in unsigned(7 downto 0);
clk:in std_logic;
dataout:out un
www.eeworm.com/read/248277/12586546
vhd counter_1024.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter_1024 is
port(clk,clr,en,updn,bcdwr:in std_logic;
datain:in std_logic_vector(9 downt
www.eeworm.com/read/110829/15524224
txt readme.txt
1. compile:
mpicc jordan.c -o jordan
2. run:
mpirun -np 4 jordan
3. result(also in file dataOut.txt):
group size: 4
Input of file "dataIn.txt"
4
1.000000 4.000000 -2.000000
www.eeworm.com/read/188087/8573597
txt readme.txt
1. compile:
mpicc qr_value.c -o qr_value -lm
2. run:
mpirun -np 3 qr_value
3. result:
Input of file "dataIn.txt"
3 3
1.000000 3.000000 4.000000
3.000000 1.00000
www.eeworm.com/read/381044/9113794
vhd fifo.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fifo is
port( DataIn :in std_logic_vector(7 downto 0);
DataOut :out std_logic_vector(7 downto 0);
clk