代码搜索：dataIn
找到约 2,888 项符合「dataIn」的源代码
代码结果 2,888
www.eeworm.com/read/17540/737694
cpld
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity ad is
port(busy:in std_logic;
datain:in unsigned(7 downto 0);
clk:in std_logic;
dataout:out unsigned
www.eeworm.com/read/17609/742561
vhd ad.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity ad is
port(busy:in std_logic;
datain:in unsigned(7 downto 0);
clk:in std_logic;
dataout:out unsigned
www.eeworm.com/read/17812/761126
v eth_registers.v
`include "eth_defines.v"
`include "timescale.v"
module eth_registers( DataIn, Address, Rw, Cs, Clk, Reset, DataOut,
r_RecSmall, r_Pad, r_HugEn, r_CrcEn, r_DlyCrcEn,
www.eeworm.com/read/17870/763194
v eth_registers.v
`include "eth_defines.v"
`include "timescale.v"
module eth_registers( DataIn, Address, Rw, Cs, Clk, Reset, DataOut,
r_RecSmall, r_Pad, r_HugEn, r_CrcEn, r_DlyCrcEn,
www.eeworm.com/read/17893/765612
v eth_registers.v
`include "eth_defines.v"
`include "timescale.v"
module eth_registers( DataIn, Address, Rw, Cs, Clk, Reset, DataOut,
r_RecSmall, r_Pad, r_HugEn, r_CrcEn, r_DlyCrcEn,
www.eeworm.com/read/17895/766144
vhd ad.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity ad is
port(busy:in std_logic;
datain:in unsigned(7 downto 0);
clk:in std_logic;
dataout:out unsigned
www.eeworm.com/read/17921/767121
vhd ad.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity ad is
port(busy:in std_logic;
datain:in unsigned(7 downto 0);
clk:in std_logic;
dataout:out unsigned
www.eeworm.com/read/18022/770850
vhd controller.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY controller IS
PORT(clk:IN STD_LOGIC;
datain:IN STD_LOGIC;
ad:OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
freq:OUT STD_LOGIC_VECTOR
www.eeworm.com/read/18031/771376
vhd ad.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity ad is
port(busy:in std_logic;
datain:in unsigned(7 downto 0);
clk:in std_logic;
dataout:out unsigned
www.eeworm.com/read/18104/774838
v eth_registers.v
`include "eth_defines.v"
`include "timescale.v"
module eth_registers( DataIn, Address, Rw, Cs, Clk, Reset, DataOut,
r_RecSmall, r_Pad, r_HugEn, r_CrcEn, r_DlyCrcEn,