代码搜索：dataIn

找到约 2,888 项符合「dataIn」的源代码

代码结果 2,888
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
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vhd code.vhd

-- code library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity code is port( datain : in unsigned(7 downto 0); da
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vhd code.vhd

-- code library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity code is port( datain : in unsigned(7 downto 0); da
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hier_info siso4_1.hier_info

|siso4_1 clk => q[0].CLK clk => q[1].CLK clk => q[2].CLK clk => q[3].CLK din => q[0].DATAIN dout
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hier_info siso4_2.hier_info

|siso4_2 clk => q[0].CLK clk => q[1].CLK clk => q[2].CLK clk => q[3].CLK din => q[0].DATAIN dout
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hier_info siso4_1.hier_info

|siso4_1 clk => q[0].CLK clk => q[1].CLK clk => q[2].CLK clk => q[3].CLK din => q[0].DATAIN dout
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hier_info siso4_2.hier_info

|siso4_2 clk => q[0].CLK clk => q[1].CLK clk => q[2].CLK clk => q[3].CLK din => q[0].DATAIN dout
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hier_info cudaqi.hier_info

|cudaqi d => q~reg0.DATAIN clk => q~reg0.CLK q
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hier_info siso4_1.hier_info

|siso4_1 clk => q[0].CLK clk => q[1].CLK clk => q[2].CLK clk => q[3].CLK din => q[0].DATAIN dout
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hier_info siso4_2.hier_info

|siso4_2 clk => q[0].CLK clk => q[1].CLK clk => q[2].CLK clk => q[3].CLK din => q[0].DATAIN dout
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h t3.h

/* This is a test for maxidx: rmup */ #define NX 16 #define FNAME "t3" #define MAXERROR 0 #pragma DATA_SECTION (x,".datain") DATA x[NX] ={ 0, 2048, 4096, 6144, 8192, 10240, 12288, 14336, 16384, 18432
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