代码搜索：dataIn
找到约 2,888 项符合「dataIn」的源代码
代码结果 2,888
www.eeworm.com/read/338256/3319347
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity io_buf_tri is
port(
datain : in vl_logic;
dataout : out vl_logic;
oe : in vl_logi
www.eeworm.com/read/323894/3507349
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity hssi_fifo is
generic(
channel_width : integer := 1
);
port(
datain : in vl_logic_vector;
clk0
www.eeworm.com/read/303435/3811358
main sukdmig3d.su.main
SUKDMIG3D - Kirchhoff Depth Migration of 3D poststack/prestack data
sukdmig3d datain= dataout= [parameters]
Required parameters:
ttfile file for input tttables
Optional
www.eeworm.com/read/278121/4147694
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cycloneii_routing_wire is
port(
datain : in vl_logic;
dataout : out vl_logic
);
end cycloneii_routing_
www.eeworm.com/read/278121/4147744
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity hssi_fifo is
generic(
channel_width : integer := 1
);
port(
datain : in vl_logic_vector;
clk0
www.eeworm.com/read/427629/1968957
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity hssi_fifo is
generic(
channel_width : integer := 1
);
port(
datain : in vl_logic_vector;
clk0
www.eeworm.com/read/427629/1969063
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity hssi_fifo is
generic(
channel_width : integer := 1
);
port(
datain : in vl_logic_vector;
clk0
www.eeworm.com/read/427629/1969203
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity hssi_fifo is
generic(
channel_width : integer := 1
);
port(
datain : in vl_logic_vector;
clk0
www.eeworm.com/read/427629/1969339
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity hssi_fifo is
generic(
channel_width : integer := 1
);
port(
datain : in vl_logic_vector;
clk0
www.eeworm.com/read/386605/2570020
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity hssi_fifo is
generic(
channel_width : integer := 1
);
port(
datain : in vl_logic_vector;
clk0