代码搜索：dataIn
找到约 2,888 项符合「dataIn」的源代码
代码结果 2,888
www.eeworm.com/read/268984/11112472
vhd uarttest.vhd
--============================================================================--
-- Design units : TestBench for miniUART device.
--
-- File name : UARTTest.vhd
--
-- Purpose : Implemen
www.eeworm.com/read/414311/11121239
vhd uarttest.vhd
--============================================================================--
-- Design units : TestBench for miniUART device.
--
-- File name : UARTTest.vhd
--
-- Purpose : Implemen
www.eeworm.com/read/412996/11170618
vhd dataoutmux.vhd
--****************************************************************************************************
-- Data out register for ARM core
-- Designed by Ruslan Lepetenok
-- Modified 04.12.2002
--**
www.eeworm.com/read/412996/11170694
vhd resltbitmask.vhd
--****************************************************************************************************
-- This module cleares/sets bit 0 and clears 1 of ALU bus for ARM7TDMI-S processor
-- Designed
www.eeworm.com/read/412239/11208906
vhd dataoutmux.vhd
--****************************************************************************************************
-- Data out register for ARM core
-- Designed by Ruslan Lepetenok
-- Modified 04.12.2002
--**
www.eeworm.com/read/412239/11208981
vhd resltbitmask.vhd
--****************************************************************************************************
-- This module cleares/sets bit 0 and clears 1 of ALU bus for ARM7TDMI-S processor
-- Designed
www.eeworm.com/read/248277/12585901
vhd testda.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity testda is
port(clk:in std_logic;
data:out std_logic_vector(7 downto 0);
www.eeworm.com/read/135837/13894781
vhd uarttest.vhd
--============================================================================--
-- Design units : TestBench for miniUART device.
--
-- File name : UARTTest.vhd
--
-- Purpose : Implemen
www.eeworm.com/read/236174/14029561
hier_info cmi_coder.hier_info
|cmi_coder
cmi => t[0].DATAIN
cmi => t[1].DATAIN
clk => t[0].CLK
clk => t[2].CLK
clk => nrz~reg0.CLK
clk => t[1].CLK
nrz