代码搜索：dataIn

找到约 2,888 项符合「dataIn」的源代码

代码结果 2,888
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/205721/15309068

m mute2.m

function [dataout]=mute2(datain,mute_flg,time1) % %function [dataout]=mute2(datain,mute_flg,time1) % %This function does a top or bottom mute from a constant %time value. %Input arguments are: % %time
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www.eeworm.com/read/205721/15309094

m mute.m

function [dataout]=mute(datain,mute_flg,headw1,headw2) % %function [dataout]=mute(datain,mute_flg,headw1,headw2) % %The mute let's you do a top, bottom and horizon mutes %The mute function returns a m
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www.eeworm.com/read/475934/6770089

eqn plj.map.eqn

-- Copyright (C) 1991-2005 Altera Corporation -- Your use of Altera Corporation's design tools, logic functions -- and other software and tools, and its AMPP partner logic -- functions, and any o
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www.eeworm.com/read/473234/6849478

c picusbnut.c

#include #fuses HSPLL,USBDIV,PLL5,CPUDIV1,VREGEN,NOWDT,NOPROTECT,NOLVP,NODEBUG #use delay(clock=48000000) /////////////////////////////////////////////////////////////////////////////
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www.eeworm.com/read/472904/6859621

vhd tribuffer.vhd

library ieee; use ieee.std_logic_1164.all; ------------------------------ entity tribuffer is port (oe:in std_logic; datain:in std_logic_vector(7 downto 0); dataout:out std_logic_vector(7 downt
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www.eeworm.com/read/472405/6876787

hier_info crcsend.hier_info

|crcsend sdata[0] => dtemp~26.DATAB sdata[0] => sdatam[0].DATAIN sdata[1] => dtemp~25.DATAB sdata[1] => sdatam[1].DATAIN sdata[2] => dtemp~24.DATAB sdata[2] => sdatam[2].DATAIN sdata[3] => dtem
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www.eeworm.com/read/392763/8327833

hier_info input.hier_info

|input en => comb~60.IN0 en => comb~49.OUTPUTSELECT en => comb~42.OUTPUTSELECT en => comb~3.OUTPUTSELECT en => comb~22.OUTPUTSELECT en => comb~33.IN0 en => comb~34.OUTPUTSELECT en => comb~61.O
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www.eeworm.com/read/173063/9676178

hier_info f4.hier_info

|F4 ENADD inst.ACLR CLR => inst4.ACLR CLR => inst5.ACLR CLR => inst6.ACLR CLR => inst2.ACLR CLK => inst.CLK CLK => inst4.CLK CLK => inst5.CLK CLK =>
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www.eeworm.com/read/171518/9747642

vhd dataoutmux.vhd

--**************************************************************************************************** -- Data out register for ARM core -- Designed by Ruslan Lepetenok -- Modified 04.12.2002 --**
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www.eeworm.com/read/171518/9747709

vhd resltbitmask.vhd

--**************************************************************************************************** -- This module cleares/sets bit 0 and clears 1 of ALU bus for ARM7TDMI-S processor -- Designed
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