代码搜索：dataIn

找到约 2,888 项符合「dataIn」的源代码

代码结果 2,888
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/17753/755820

hier_info myfx2.hier_info

|MYFX2 nRESET => ~NO_FANOUT~ PA[0] => RAMBA[9].DATAIN PA[1] => RAMBA[10].DATAIN PA[2] => RAMBA[11].DATAIN PA[3] => RAMBA[12].DATAIN PA[4] => RAMBA[13].DATAIN PA[5] => RAMBA[14].DATAIN PA[6] =>
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www.eeworm.com/read/418415/2089244

hier_info myfx2.hier_info

|MYFX2 nRESET => ~NO_FANOUT~ PA[0] => RAMBA[9].DATAIN PA[1] => RAMBA[10].DATAIN PA[2] => RAMBA[11].DATAIN PA[3] => RAMBA[12].DATAIN PA[4] => RAMBA[13].DATAIN PA[5] => RAMBA[14].DATAIN PA[6] =>
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www.eeworm.com/read/416314/2124900

hier_info myfx2.hier_info

|MYFX2 nRESET => ~NO_FANOUT~ PA[0] => RAMBA[9].DATAIN PA[1] => RAMBA[10].DATAIN PA[2] => RAMBA[11].DATAIN PA[3] => RAMBA[12].DATAIN PA[4] => RAMBA[13].DATAIN PA[5] => RAMBA[14].DATAIN PA[6] =>
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www.eeworm.com/read/188684/8519675

vhd hanmin_cd.vhd

-- Hamming Encoder -- A 4-bit Hamming Code encoder using concurrent assignments. -- The output vector is connected to the individual parity bits using an aggregate assignment. -- download from: w
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www.eeworm.com/read/431944/8645713

vwf sdh.vwf

/* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to
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www.eeworm.com/read/429004/8824737

v map_lpm_ram.v

module map_lpm_ram(dataout,datain,addr,we,inclk,outclk); input[15:0] datain; input[7:0] addr; input we,inclk,outclk; output[15:0] dataout; lpm_ram_dq ram(.data(datain),.address(addr),.we(we),.i
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www.eeworm.com/read/384201/8891004

v map_lpm_ram.v

module map_lpm_ram(dataout,datain,addr,we,inclk,outclk); input[15:0] datain; input[7:0] addr; input we,inclk,outclk; output[15:0] dataout; lpm_ram_dq ram(.data(datain),.address(addr),.we(we),.i
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www.eeworm.com/read/383822/8915407

v map_lpm_ram.v

module map_lpm_ram(dataout,datain,addr,we,inclk,outclk); input[15:0] datain; input[7:0] addr; input we,inclk,outclk; output[15:0] dataout; lpm_ram_dq ram(.data(datain),.address(addr),.we(we),.i
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www.eeworm.com/read/281861/9128813

vhd ledmux.vhd

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY ledmux IS PORT( datain : IN STD_LOGIC_VECTOR(29 DOWNTO 0); --输入数据 ledaddr : IN STD_LOGIC_VECTOR(2 DOWNTO 0); --地址 dataout :
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www.eeworm.com/read/183801/9137824

txt readme.txt

/*由于操作控制板的原理图对FPGA管脚的定义和这里的HDL文件定义的名称有所不同 // 因此列表说明 FPGA313CAKZ.V 313CP3PCB -clk_in, FLEXCLK -switchin[7], D7 -switchin[6], D6 -switchin[5], D5
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