代码搜索:dataIn

找到约 2,888 项符合「dataIn」的源代码

代码结果 2,888
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txt 6.3.5快速排序.txt

DATS EQU 20H N EQU 5DH QUEUE EQU 1FH F DATA 3CH R DATA 3DH TST: MOV DPTR,#LIST MOV P2,#DATS MOV R0,#0 MOV R2,#N CPY: CLR A MOVC A,@A+DPTR MOVX @R0,A INC DPTR
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txt 6.3.5快速排序.txt

DATS EQU 20H N EQU 5DH QUEUE EQU 1FH F DATA 3CH R DATA 3DH TST: MOV DPTR,#LIST MOV P2,#DATS MOV R0,#0 MOV R2,#N CPY: CLR A MOVC A,@A+DPTR MOVX @R0,A INC DPTR
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v ddr_sdram.v

/****************************************************************************** * * LOGIC CORE: DDR SDRAM Controller * MODULE NAME: ddr_sdram() * COMPANY: No
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vhd jsq24.vhd

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; ENTITY jsq24 IS PORT(clk:IN STD_LOGIC; en0,en1,cin:IN STD_LOGIC; data
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edf jsq60.edf

(edif jsq60 (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0)) (status (written (timeStamp 2006 11 23 10 36 2) (author "Synplicity, Inc.") (program "
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vhd ad.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity ad is port(busy:in std_logic; datain:in unsigned(7 downto 0); clk:in std_logic; dataout:out unsigned
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vhd ad.vhd

--AD library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity ad is port(busy:in std_logic; datain:in unsigned(7 downto 0); clk:in std_logic; dataout:out un
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txt structural description of an 8-bit shift register.txt

Structural Description of an 8-bit Shift Register ENTITY dtff IS GENERIC(initial : BIT := '1'); --initial value of q PORT(d, clock : IN BIT; q : BUFFER BIT := initial); END dtff; ARCHITECTURE z
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html resamp.html

/ [Master Index] [Index for ./main] resamp (./main/resamp.m) Function Synopsis [datao
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html mat2asc.html

/ [Master Index] [Index for ./main] mat2asc (./main/mat2asc.m) Function Synopsis mat2