代码搜索:ctrl
找到约 10,000 项符合「ctrl」的源代码
代码结果 10,000
www.eeworm.com/read/420624/10786044
cnf ctrl.cnf
www.eeworm.com/read/420624/10786058
vhd ctrl.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ctrl is
port(clk,spe:in std_logic;
en:out std_logic);
end;
architecture behave of ctrl is
type states is
www.eeworm.com/read/420624/10786061
sof ctrl.sof
www.eeworm.com/read/420624/10786069
mmf ctrl.mmf
www.eeworm.com/read/420624/10786116
ttf ctrl.ttf
255,255, 98,255, 37, 0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,
96, 24,134, 97, 24,134, 9
www.eeworm.com/read/420624/10786131
hif ctrl.hif
HIF003
--
-- Copyright (C) 1988-2000 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, an
www.eeworm.com/read/420624/10786137
sym ctrl.sym
www.eeworm.com/read/420624/10786150
acf ctrl.acf
--
-- Copyright (C) 1988-2000 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any
www.eeworm.com/read/467709/7000212
vhd ctrl.vhd
LIBRARY IEEE; --测频控制
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ctrl IS
PORT(CLKK:IN STD_LOGIC; --时钟1HZ
CNT_EN:OUT STD_LOGIC; --使能
RST_CNT:OUT STD_LOG
www.eeworm.com/read/467049/7014416