代码搜索:ctrl
找到约 10,000 项符合「ctrl」的源代码
代码结果 10,000
www.eeworm.com/read/286614/8755412
edn sram_ctrl.edn
(edif test (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0))
(status (written (timeStamp 2007 12 5 14 6 59)
(author "Xilinx, Inc.")
(program "Xilinx CORE Generator" (version "Xi
www.eeworm.com/read/286614/8755420
veo sram_ctrl.veo
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation,
www.eeworm.com/read/286614/8755421
asy sram_ctrl.asy
Version 4
SymbolType BLOCK
RECTANGLE Normal 32 0 320 272
PIN 0 48 LEFT 36
PINATTR PinName addr[7:0]
PINATTR Polarity IN
LINE Wide 0 48 32 48
PIN 0 240 LEFT 36
PINATTR PinName clk
PINATTR Po
www.eeworm.com/read/286614/8755455
mif sram_ctrl.mif
0000000000000000
0000000000000001
0000000000000010
0000000000000011
0000000000000100
0000000000000101
0000000000000110
0000000000000111
0000000000001000
0000000000001001
0000000000001010
00
www.eeworm.com/read/286614/8755477
vho sram_ctrl.vho
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation
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xco sram_ctrl.xco
# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = E:\modulator\modulator_fpga
SET speedgrade = -4
SET simulationfiles = Behavioral
www.eeworm.com/read/286614/8755522
sym sram_ctrl.sym
VERSION 5
BEGIN SYMBOL sram_ctrl
SYMBOLTYPE BLOCK
TIMESTAMP 2007 12 5 6 7 2
SYMPIN 0 48 Input addr[7:0]
SYMPIN 0 240 Input clk
SYMPIN 352 48 Output dout[15:0]
RECTANGLE N 32 0 320 272
BEGIN D
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vhd sram_ctrl.vhd
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation
www.eeworm.com/read/385200/8813908
v fre_ctrl.v
module fre_ctrl(clk,rst,count_en,count_clr,load);
output count_en,count_clr,load;
input clk,rst;
reg count_en,load;
always @(posedge clk)
begin
if(rst)
begin count_en=0; load=1; end
www.eeworm.com/read/429132/8817151
c ctrl_set.c
#include "inc\44b0x.h"
#include "DataType.h"
#define EXT_OSC_CLK 10000000
unsigned int MCLK = 64000000;
void ChangePllValue(int mdiv, int pdiv, int sdiv)
{
int i = 1;
rPLLCON = (m