代码搜索：construct
找到约 6,584 项符合「construct」的源代码
代码结果 6,584
www.eeworm.com/read/117181/6109539
ms hw-trap.ms
# mach(): m32r m32rx
# output(): pass\n
.include "testutils.inc"
start
; construct bra trap2_handler in trap 2 slot
ld24 r0,#bra_insn
ld r0,@r0
ld24 r1,#trap2_handler
addi r1,#-0x48 ; pc rela
www.eeworm.com/read/108102/6186279
java director.java
package com.javapatterns.builder.extended1;
public class Director
{
private Builder builder;
public Director(Builder builder)
{
this.builder = builder;
}
publ
www.eeworm.com/read/108102/6186293
java director.java
package com.javapatterns.builder.extended;
public class Director
{
private Builder builder;
public Director(Builder builder)
{
this.builder = builder;
}
publi
www.eeworm.com/read/101082/6249719
c m_tmpfil.c
/* m_tmpfil.c - construct a temporary file */
#include "../h/mh.h"
#include
char *m_tmpfil (template)
register char *template;
{
static char tmpfil[BUFSIZ];
(void) sprintf (tm
www.eeworm.com/read/101082/6250236
c m_tmpfil.c
/* m_tmpfil.c - construct a temporary file */
#include "../h/mh.h"
#include
char *m_tmpfil (template)
register char *template;
{
static char tmpfil[BUFSIZ];
(void) sprintf (tm
www.eeworm.com/read/490774/6442344
smsg adc.map.smsg
Warning (10273): Verilog HDL warning at ADC.v(132): extended using "x" or "z"
Warning (10268): Verilog HDL information at ADC.v(66): always construct contains both blocking and non-blocking assignmen
www.eeworm.com/read/488475/6487587
smsg part4.map.smsg
Warning (10273): Verilog HDL warning at part4.v(22): extended using "x" or "z"
Warning (10268): Verilog HDL information at part4.v(32): always construct contains both blocking and non-blocking assign
www.eeworm.com/read/488553/6489362
m baseonwaveletanalyse.m
%%%%%%%%%%%【基于小波系数分析主程序】%%%%%%%%%%%%%%
clear all
disp('Running WT....')
%%%%%%%%%%%%%%%【读入图像数据】%%%%%%%%%%%%%%%%%%%
load wbarb; % 下载图像
X=im2double(X);
f=X; % 原始图像
%%%%%%%%%%%%%%%【二维小波
www.eeworm.com/read/488254/6499947
smsg seqdet.map.smsg
Warning (10268): Verilog HDL information at seqdet.v(13): always construct contains both blocking and non-blocking assignments
www.eeworm.com/read/482411/6624433
smsg huang.map.smsg
Warning (10268): Verilog HDL information at huang.v(130): Always Construct contains both blocking and non-blocking assignments