代码搜索：complex

找到约 10,000 项符合「complex」的源代码

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热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
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srd complex_bibus2.srd

f "noname"; #file 0 f "c:\eda\synplicity\fpga_81\lib\altera\altera.v"; #file 1 f "c:\eda\synplicity\fpga_81\lib\altera\cycloneii.v"; #file 2 f "c:\eda\synplicity\fpga_81\lib\altera\altera_mf.v"; #f
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tcl complex_bibus2.tcl

# Run with quartus_sh -t set_global_assignment -name ROOT "|complex_bibus" set_global_assignment -name FAMILY "CYCLONE II" set_global_assignment -name DEVICE "EP2C5Q208C6" set_global_
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areasrr rpt_complex_bibus.areasrr

#### START OF AREA REPORT #####[ Part: EP2C5QC208-6 (Altera) ----------------------------------------------------------------------------- ######## Utilization report for Top level view:
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tlg complex_bibus2.tlg

Selecting top level module complex_bibus @N:"C:\prj\Example-5-1\complex_bibus\decode.v":1:7:1:12|Synthesizing module decode @N:"C:\prj\Example-5-1\complex_bibus\counter.v":2:7:2:13|Synthesizing mo
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srr complex_bibus2.srr

#Program: Synplify Pro 8.1 #OS: Windows_NT $ Start of Compile #Mon Jan 02 21:43:33 2006 Synplicity Verilog Compiler, version 3.1.0, Build 049R, built May 3 2005 Copyright (C) 1994-2005, Synp
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vif complex_bibus2.vif

# # Synplicity Verification Interface File # Generated using Synplify-pro # # Copyright (c) 1996-2005 Synplicity, Inc. # All rights reserved # # Set logfile options vif_set_result_file comp
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xrf complex_bibus2.xrf

vendor_name = Synplicity source_file = 0, noname, synplify source_file = 1, c:\eda\synplicity\fpga_81\lib\altera\altera.v, synplify source_file = 2, c:\eda\synplicity\fpga_81\lib\altera\cycloneii.v
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srs complex_bibus2.srs

# # # # Created by Synplify Verilog HDL Compiler version 3.1.0, Build 049R from Synplicity, Inc. # Copyright 1994-2004 Synplicity, Inc. , All rights reserved. # Synthesis Netlist written on Mon J
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sxr complex_bibus2.sxr

BeginView complex_bibus NoName Inst: I_16_x_i I_16_x_i_cZ inv Inst: un1_decode_out_2_0[4] un1_decode_out_2_0_4_ cycloneii_lcell_comb Inst: un1_decode_out_2_0[5] un1_decode_out_2_0_5_ cycl
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sdc autoconstraint_complex_bibus.sdc

#Begin clock constraint define_clock -name {b:complex_bibus|clk} -period 10000000.000 -clockgroup Autoconstr_clkgroup_0 -rise 0.000 -fall 5000000.000 -route 0.000 #End clock constraint
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