代码搜索：complex
找到约 10,000 项符合「complex」的源代码
代码结果 10,000
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v complex_bibus2.v
module complex_bibus (clk, rst, sel1, sel2, sel3, data_bus, addr);
input clk, rst;
input sel1, sel2, sel3;
input [7:0] addr;
inout [7:0] data_bus;
wire [7:0] data_in;
//wire [7:0]
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srm complex_bibus2.srm
@ERMRq pa)qq_uR XOCFs_RVVuv)Q;O
NR 3#HPb_E_8DkR#C4N;
PHR3#Hbsl;R4
RNP#_$MVOFsCC_#Js_bH"lRO"D ;P
NRE3P8#D_ RHb4F;
R
J;HDRO N;
H$R#M#_HOODF ;R4
OHRD
s;N#HR$NM_#O$ME;R4
bHRsCC#0N;
H$R#M#_N$EMO
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plg complex_bibus2.plg
@P: Part : EP2C5QC208-6
@P: Worst Slack : NA
@P: complex_bibus Part : ep2c5qc208-6
@P: complex_bibus I/O ATOMs : 21
@P: complex_bibus DSP Blocks : 0 (0 nine bit DSP elements)
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tcl complex_bibus_rm.tcl
set_global_assignment -name ROOT "|complex_bibus" -remove
set_global_assignment -name FAMILY -remove
set_global_assignment -section_id clk_setting -name DUTY_CYCLE "50.00" -remove
set_instance_a
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fse complex_bibus2.fse
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vqm complex_bibus2.vqm
//
// Written by Synplify
// Synplify 8.1.0, Build 539R.
// Mon Jan 02 21:43:34 2006
//
// Source file index table:
// Object locations will have the form :
// file 0 "noname"
// f
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srd complex_bibus2.srd
f "noname"; #file 0
f "c:\eda\synplicity\fpga_81\lib\altera\altera.v"; #file 1
f "c:\eda\synplicity\fpga_81\lib\altera\cycloneii.v"; #file 2
f "c:\eda\synplicity\fpga_81\lib\altera\altera_mf.v"; #f
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tcl complex_bibus2.tcl
# Run with quartus_sh -t
set_global_assignment -name ROOT "|complex_bibus"
set_global_assignment -name FAMILY "CYCLONE II"
set_global_assignment -name DEVICE "EP2C5Q208C6"
set_global_
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areasrr rpt_complex_bibus.areasrr
#### START OF AREA REPORT #####[
Part: EP2C5QC208-6 (Altera)
-----------------------------------------------------------------------------
######## Utilization report for Top level view:
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tlg complex_bibus2.tlg
Selecting top level module complex_bibus
@N:"C:\prj\Example-5-1\complex_bibus\decode.v":1:7:1:12|Synthesizing module decode
@N:"C:\prj\Example-5-1\complex_bibus\counter.v":2:7:2:13|Synthesizing mo