代码搜索：complex

找到约 10,000 项符合「complex」的源代码

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h gsl_fft_complex.h

/* fft/gsl_fft_complex.h * * Copyright (C) 1996, 1997, 1998, 1999, 2000 Brian Gough * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU Gene
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h gsl_dft_complex.h

/* fft/gsl_dft_complex.h * * Copyright (C) 1996, 1997, 1998, 1999, 2000 Brian Gough * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU Gene
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c test_complex_source.c

/* fft/test_complex.c * * Copyright (C) 1996, 1997, 1998, 1999, 2000 Brian Gough * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General
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h gsl_complex_math.h

/* complex/gsl_complex_math.h * * Copyright (C) 1996, 1997, 1998, 1999, 2000 Jorma Olavi T鋒tinen, Brian Gough * * This program is free software; you can redistribute it and/or modify * it under
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c test_complex_io.c

/* vector/test_complex_io.c * * Copyright (C) 1996, 1997, 1998, 1999, 2000 Gerard Jungman, Brian Gough * * This program is free software; you can redistribute it and/or modify * it under the te
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h gsl_vector_complex.h

#ifndef __GSL_VECTOR_COMPLEX_H__ #define __GSL_VECTOR_COMPLEX_H__ #define GSL_VECTOR_REAL(z, i) ((z)->data[2*(i)*(z)->stride]) #define GSL_VECTOR_IMAG(z, i) ((z)->data[2*(i)*(z)->stride + 1]) #i
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c test_complex_source.c

/* vector/test_complex_source.c * * Copyright (C) 1996, 1997, 1998, 1999, 2000 Gerard Jungman, Brian Gough * * This program is free software; you can redistribute it and/or modify * it under th
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c test_complex_source.c

/* matrix/test_complex_source.c * * Copyright (C) 1996, 1997, 1998, 1999, 2000 Gerard Jungman, Brian Gough * * This program is free software; you can redistribute it and/or modify * it under th
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m rec_frommag_complex.m

function g=rec_frommag_complex(M,I,N); %------------------------------------------------------------------------------ % rec_frommag_complex.m % This function generate the fourth order cross cumula
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v complex_bibus2.v

module complex_bibus (clk, rst, sel1, sel2, sel3, data_bus, addr); input clk, rst; input sel1, sel2, sel3; input [7:0] addr; inout [7:0] data_bus; wire [7:0] data_in; //wire [7:0]
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