代码搜索：complex

找到约 10,000 项符合「complex」的源代码

代码结果 10,000
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/14659/401663

srr complex_bibus.srr

#Program: Synplify Pro 8.1 #OS: Windows_NT $ Start of Compile #Mon Jan 02 21:43:56 2006 Synplicity Verilog Compiler, version 3.1.0, Build 049R, built May 3 2005 Copyright (C) 1994-2005, Synp
·
www.eeworm.com/read/14659/401665

sxr complex_bibus.sxr

BeginView complex_bibus NoName Inst: I_32_x_i I_32_x_i_cZ inv Inst: un1_decode_out_iv_0[4] un1_decode_out_iv_0_4_ cycloneii_lcell_comb Inst: un1_decode_out_iv_0[5] un1_decode_out_iv_0_5_
·
www.eeworm.com/read/14659/401667

vif complex_bibus.vif

# # Synplicity Verification Interface File # Generated using Synplify-pro # # Copyright (c) 1996-2005 Synplicity, Inc. # All rights reserved # # Set logfile options vif_set_result_file comp
·
www.eeworm.com/read/14659/401672

srm complex_bibus.srm

@ERMRq pa)qq_uR XOCFs_RVVuv)Q;O NR 3#HPb_E_8DkR#C4N; PHR3#Hbsl;R4 RNP#_$MVOFsCC_#Js_bH"lRO"D ;P NRE3P8#D_ RHb4F; R J;HDRO N; H$R#M#_HOODF ;R4 OHRD s;N#HR$NM_#O$ME;R4 bHRsCC#0N; H$R#M#_N$EMO
·
www.eeworm.com/read/14659/401676

xrf complex_bibus.xrf

vendor_name = Synplicity source_file = 0, noname, synplify source_file = 1, c:\eda\synplicity\fpga_81\lib\altera\altera.v, synplify source_file = 2, c:\eda\synplicity\fpga_81\lib\altera\cycloneii.v
·
www.eeworm.com/read/14659/401678

srd complex_bibus.srd

f "noname"; #file 0 f "c:\eda\synplicity\fpga_81\lib\altera\altera.v"; #file 1 f "c:\eda\synplicity\fpga_81\lib\altera\cycloneii.v"; #file 2 f "c:\eda\synplicity\fpga_81\lib\altera\altera_mf.v"; #f
·
www.eeworm.com/read/16498/673291

xco complex_mult.xco

# BEGIN Project Options SET flowvendor = Foundation_iSE SET vhdlsim = True SET verilogsim = True SET workingdirectory = C:\work\ISE\c11 SET speedgrade = -12 SET simulationfiles = Behavioral SET asysym
·
www.eeworm.com/read/17578/739808

xco complex_mult.xco

# BEGIN Project Options SET flowvendor = Foundation_iSE SET vhdlsim = True SET verilogsim = True SET workingdirectory = C:\work\ISE\c11 SET speedgrade = -12 SET simulationfiles = Behavioral SET asysym
·
www.eeworm.com/read/17872/763754

xco complex_mult.xco

# BEGIN Project Options SET flowvendor = Foundation_iSE SET vhdlsim = True SET verilogsim = True SET workingdirectory = C:\work\ISE\c11 SET speedgrade = -12 SET simulationfiles = Behavioral SET asysym
·
www.eeworm.com/read/18163/778475

xco complex_mult.xco

# BEGIN Project Options SET flowvendor = Foundation_iSE SET vhdlsim = True SET verilogsim = True SET workingdirectory = C:\work\ISE\c11 SET speedgrade = -12 SET simulationfiles = Behavioral SET asysym
·