代码搜索：checking
找到约 6,492 项符合「checking」的源代码
代码结果 6,492
www.eeworm.com/read/17609/742691
vhd rxd3.vhd
--v1.0 rxd databit 8 none checking
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity rxd3 is
port(clk,rx:in std_logic;
sig1:buffer std_logic;
q:out std_log
www.eeworm.com/read/17895/766274
vhd rxd3.vhd
--v1.0 rxd databit 8 none checking
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity rxd3 is
port(clk,rx:in std_logic;
sig1:buffer std_logic;
q:out std_log
www.eeworm.com/read/17921/767251
vhd rxd3.vhd
--v1.0 rxd databit 8 none checking
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity rxd3 is
port(clk,rx:in std_logic;
sig1:buffer std_logic;
q:out std_log
www.eeworm.com/read/18031/771506
vhd rxd3.vhd
--v1.0 rxd databit 8 none checking
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity rxd3 is
port(clk,rx:in std_logic;
sig1:buffer std_logic;
q:out std_log
www.eeworm.com/read/18253/782455
vhd rxd3.vhd
--v1.0 rxd databit 8 none checking
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity rxd3 is
port(clk,rx:in std_logic;
sig1:buffer std_logic;
q:out std_log
www.eeworm.com/read/18342/784874
vhd rxd3.vhd
--v1.0 rxd databit 8 none checking
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity rxd3 is
port(clk,rx:in std_logic;
sig1:buffer std_logic;
q:out std_log
www.eeworm.com/read/18488/791174
vhd rxd3.vhd
--v1.0 rxd databit 8 none checking
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity rxd3 is
port(clk,rx:in std_logic;
sig1:buffer std_logic;
q:out std_log
www.eeworm.com/read/296366/3904376
vhd rxd3.vhd
--v1.0 rxd databit 8 none checking
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity rxd3 is
port(clk,rx:in std_logic;
sig1:buffer std_logic;
q:out std_log
www.eeworm.com/read/248277/12586272
vhd rxd3.vhd
--v1.0 rxd databit 8 none checking
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity rxd3 is
port(clk,rx:in std_logic;
sig1:buffer std_logic;
q:out std_log